Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	69637932	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24885018

1

T1

325

T2

60886

T3

93

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	87653183	1			T1	1474		T2	231913		T3	5907
values[0x0]	3250413	1			T1	117		T2	1458		T3	110
values[0x1]	3619354	1			T1	113		T2	1444		T3	77

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48350465	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

46172485

1

T1

726

T2

110712

T3

2071

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	336004	1			T1	15		T2	944		T3	22
valid_sources[0x01]	350798	1			T1	6		T2	912		T3	18
valid_sources[0x02]	371011	1			T1	18		T2	926		T3	17
valid_sources[0x03]	387156	1			T1	6		T2	951		T3	22
valid_sources[0x04]	335047	1			T1	5		T2	865		T3	25
valid_sources[0x05]	340667	1			T1	5		T2	943		T3	30
valid_sources[0x06]	333317	1			T1	1		T2	919		T3	27
valid_sources[0x07]	331675	1			T1	3		T2	906		T3	18
valid_sources[0x08]	344350	1			T1	10		T2	886		T3	28
valid_sources[0x09]	384844	1			T1	2		T2	821		T3	22
valid_sources[0x0a]	329475	1			T1	6		T2	948		T3	18
valid_sources[0x0b]	335735	1			T1	2		T2	942		T3	19
valid_sources[0x0c]	351929	1			T1	14		T2	962		T3	31
valid_sources[0x0d]	347408	1			T1	11		T2	962		T3	19
valid_sources[0x0e]	358031	1			T1	7		T2	887		T3	29
valid_sources[0x0f]	363347	1			T1	18		T2	948		T3	15
valid_sources[0x10]	360269	1			T1	16		T2	915		T3	25
valid_sources[0x11]	411082	1			T1	8		T2	931		T3	25
valid_sources[0x12]	325824	1			T1	6		T2	927		T3	26
valid_sources[0x13]	354317	1			T1	1		T2	896		T3	25
valid_sources[0x14]	334537	1			T1	7		T2	933		T3	27
valid_sources[0x15]	417910	1			T1	7		T2	921		T3	19
valid_sources[0x16]	540242	1			T1	4		T2	930		T3	16
valid_sources[0x17]	382815	1			T1	8		T2	928		T3	25
valid_sources[0x18]	328683	1			T1	6		T2	916		T3	24
valid_sources[0x19]	353369	1			T1	12		T2	967		T3	25
valid_sources[0x1a]	357930	1			T1	1		T2	847		T3	25
valid_sources[0x1b]	314774	1			T1	4		T2	899		T3	22
valid_sources[0x1c]	376190	1			T1	9		T2	930		T3	25
valid_sources[0x1d]	352647	1			T1	9		T2	886		T3	26
valid_sources[0x1e]	369513	1			T1	3		T2	940		T3	23
valid_sources[0x1f]	319965	1			T1	5		T2	915		T3	38
valid_sources[0x20]	336926	1			T1	12		T2	883		T3	25
valid_sources[0x21]	420999	1			T1	7		T2	929		T3	32
valid_sources[0x22]	401619	1			T1	10		T2	867		T3	24
valid_sources[0x23]	373064	1			T1	2		T2	916		T3	22
valid_sources[0x24]	369135	1			T1	4		T2	920		T3	24
valid_sources[0x25]	430596	1			T1	4		T2	927		T3	24
valid_sources[0x26]	364759	1			T1	11		T2	869		T3	32
valid_sources[0x27]	359286	1			T1	17		T2	930		T3	20
valid_sources[0x28]	344739	1			T1	14		T2	853		T3	21
valid_sources[0x29]	486586	1			T1	6		T2	974		T3	20
valid_sources[0x2a]	335089	1			T1	3		T2	916		T3	29
valid_sources[0x2b]	328611	1			T1	3		T2	928		T3	20
valid_sources[0x2c]	379013	1			T2	922		T3	19		T4	82
valid_sources[0x2d]	354962	1			T1	6		T2	869		T3	18
valid_sources[0x2e]	362612	1			T1	7		T2	931		T3	24
valid_sources[0x2f]	378056	1			T1	2		T2	911		T3	24
valid_sources[0x30]	372547	1			T1	12		T2	944		T3	24
valid_sources[0x31]	380819	1			T1	9		T2	874		T3	39
valid_sources[0x32]	337984	1			T1	11		T2	924		T3	28
valid_sources[0x33]	392200	1			T1	10		T2	963		T3	19
valid_sources[0x34]	345778	1			T1	9		T2	906		T3	27
valid_sources[0x35]	396628	1			T1	1		T2	914		T3	22
valid_sources[0x36]	350161	1			T1	8		T2	894		T3	32
valid_sources[0x37]	342182	1			T1	12		T2	895		T3	22
valid_sources[0x38]	330807	1			T1	6		T2	957		T3	22
valid_sources[0x39]	381073	1			T1	2		T2	961		T3	35
valid_sources[0x3a]	342781	1			T1	7		T2	898		T3	25
valid_sources[0x3b]	368641	1			T1	15		T2	895		T3	26
valid_sources[0x3c]	345399	1			T1	8		T2	961		T3	23
valid_sources[0x3d]	338933	1			T1	3		T2	912		T3	26
valid_sources[0x3e]	366089	1			T1	8		T2	911		T3	37
valid_sources[0x3f]	360880	1			T1	8		T2	928		T3	27
valid_sources[0x40]	343716	1			T1	4		T2	919		T3	28
valid_sources[0x41]	402900	1			T1	6		T2	907		T3	29
valid_sources[0x42]	368479	1			T1	10		T2	854		T3	23
valid_sources[0x43]	399828	1			T1	5		T2	983		T3	29
valid_sources[0x44]	491825	1			T1	9		T2	906		T3	22
valid_sources[0x45]	354856	1			T1	6		T2	886		T3	23
valid_sources[0x46]	350810	1			T1	4		T2	984		T3	20
valid_sources[0x47]	406901	1			T1	2		T2	943		T3	27
valid_sources[0x48]	468370	1			T1	4		T2	932		T3	19
valid_sources[0x49]	353911	1			T1	11		T2	863		T3	19
valid_sources[0x4a]	370768	1			T1	3		T2	939		T3	25
valid_sources[0x4b]	371787	1			T1	3		T2	937		T3	17
valid_sources[0x4c]	442790	1			T1	6		T2	889		T3	22
valid_sources[0x4d]	491541	1			T1	7		T2	899		T3	27
valid_sources[0x4e]	399892	1			T1	2		T2	926		T3	23
valid_sources[0x4f]	358033	1			T1	3		T2	890		T3	29
valid_sources[0x50]	322079	1			T1	5		T2	917		T3	19
valid_sources[0x51]	325933	1			T1	6		T2	835		T3	31
valid_sources[0x52]	408955	1			T1	3		T2	916		T3	26
valid_sources[0x53]	325406	1			T1	6		T2	960		T3	27
valid_sources[0x54]	397421	1			T1	6		T2	902		T3	27
valid_sources[0x55]	458025	1			T1	5		T2	906		T3	21
valid_sources[0x56]	345090	1			T1	2		T2	950		T3	27
valid_sources[0x57]	353213	1			T1	2		T2	926		T3	29
valid_sources[0x58]	368917	1			T1	6		T2	911		T3	22
valid_sources[0x59]	381963	1			T1	7		T2	863		T3	31
valid_sources[0x5a]	361630	1			T1	11		T2	903		T3	31
valid_sources[0x5b]	366148	1			T1	6		T2	924		T3	24
valid_sources[0x5c]	366139	1			T1	4		T2	870		T3	16
valid_sources[0x5d]	353883	1			T1	3		T2	920		T3	18
valid_sources[0x5e]	346852	1			T1	1		T2	922		T3	14
valid_sources[0x5f]	353505	1			T1	10		T2	1053		T3	18
valid_sources[0x60]	347041	1			T1	6		T2	885		T3	36
valid_sources[0x61]	387063	1			T1	3		T2	927		T3	18
valid_sources[0x62]	339868	1			T1	8		T2	950		T3	29
valid_sources[0x63]	363394	1			T1	3		T2	938		T3	24
valid_sources[0x64]	365149	1			T1	7		T2	886		T3	22
valid_sources[0x65]	333173	1			T2	873		T3	22		T4	102
valid_sources[0x66]	346196	1			T1	11		T2	951		T3	21
valid_sources[0x67]	385354	1			T1	6		T2	897		T3	20
valid_sources[0x68]	344932	1			T1	4		T2	958		T3	31
valid_sources[0x69]	344890	1			T1	15		T2	926		T3	25
valid_sources[0x6a]	331860	1			T1	12		T2	889		T3	21
valid_sources[0x6b]	335434	1			T1	3		T2	971		T3	22
valid_sources[0x6c]	342234	1			T1	9		T2	881		T3	20
valid_sources[0x6d]	346064	1			T1	7		T2	950		T3	24
valid_sources[0x6e]	345188	1			T1	3		T2	900		T3	25
valid_sources[0x6f]	386477	1			T1	4		T2	915		T3	18
valid_sources[0x70]	342137	1			T1	7		T2	950		T3	20
valid_sources[0x71]	318383	1			T1	11		T2	924		T3	24
valid_sources[0x72]	376060	1			T1	5		T2	887		T3	27
valid_sources[0x73]	361018	1			T1	6		T2	907		T3	25
valid_sources[0x74]	457040	1			T1	9		T2	943		T3	22
valid_sources[0x75]	348447	1			T1	8		T2	908		T3	36
valid_sources[0x76]	346861	1			T1	8		T2	959		T3	25
valid_sources[0x77]	363089	1			T1	9		T2	960		T3	23
valid_sources[0x78]	393132	1			T1	4		T2	850		T3	19
valid_sources[0x79]	340492	1			T1	9		T2	972		T3	24
valid_sources[0x7a]	358367	1			T1	8		T2	918		T3	31
valid_sources[0x7b]	360945	1			T1	4		T2	917		T3	17
valid_sources[0x7c]	335361	1			T1	6		T2	948		T3	19
valid_sources[0x7d]	341385	1			T1	3		T2	904		T3	25
valid_sources[0x7e]	338765	1			T1	10		T2	901		T3	27
valid_sources[0x7f]	429790	1			T1	2		T2	879		T3	29
valid_sources[0x80]	444204	1			T1	7		T2	889		T3	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18883720

1

T1

232

T2

60153

T3

25

values[0x0]

all_enables

biggest_size

3026317

1

T1

53

T2

486

T3

46

values[0x1]

all_enables

biggest_size

2974981

1

T1

40

T2

247

T3

22