Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	9819540	0	0
ctrl_rd_A	2147483647	185417	0	0
intr_enable_rd_A	2147483647	162318	0	0
ovrd_rd_A	2147483647	183266	0	0
timeout_ctrl_rd_A	2147483647	183216	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9819540	0	0
T11	332284	0	0	0
T12	842815	332047	0	0
T14	238788	0	0	0
T15	223857	36125	0	0
T16	0	374573	0	0
T20	0	92795	0	0
T23	111388	0	0	0
T24	1266	0	0	0
T25	851	0	0	0
T30	0	351961	0	0
T31	0	172241	0	0
T32	0	5080	0	0
T33	0	104504	0	0
T34	0	251356	0	0
T35	0	56496	0	0
T36	789348	0	0	0
T37	787847	0	0	0
T38	276286	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	185417	0	0
T11	332284	0	0	0
T12	842815	0	0	0
T14	238788	0	0	0
T15	223857	4569	0	0
T23	111388	0	0	0
T24	1266	0	0	0
T25	851	0	0	0
T33	0	4807	0	0
T36	789348	0	0	0
T37	787847	0	0	0
T38	276286	0	0	0
T47	0	3016	0	0
T48	0	29587	0	0
T91	0	3466	0	0
T92	0	4717	0	0
T93	0	1828	0	0
T94	0	4120	0	0
T95	0	1902	0	0
T96	0	6544	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	162318	0	0
T11	332284	0	0	0
T12	842815	0	0	0
T14	238788	0	0	0
T15	223857	3987	0	0
T23	111388	0	0	0
T24	1266	0	0	0
T25	851	0	0	0
T33	0	4371	0	0
T36	789348	0	0	0
T37	787847	0	0	0
T38	276286	0	0	0
T91	0	2956	0	0
T92	0	4184	0	0
T93	0	1540	0	0
T94	0	3610	0	0
T95	0	1533	0	0
T97	0	21	0	0
T98	0	22	0	0
T99	0	24	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	183266	0	0
T11	332284	0	0	0
T12	842815	0	0	0
T14	238788	0	0	0
T15	223857	4573	0	0
T23	111388	0	0	0
T24	1266	0	0	0
T25	851	0	0	0
T33	0	4793	0	0
T36	789348	0	0	0
T37	787847	0	0	0
T38	276286	0	0	0
T47	0	2998	0	0
T48	0	29898	0	0
T91	0	3575	0	0
T92	0	4814	0	0
T93	0	1662	0	0
T94	0	4140	0	0
T95	0	1832	0	0
T96	0	5995	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	183216	0	0
T11	332284	0	0	0
T12	842815	0	0	0
T14	238788	0	0	0
T15	223857	4268	0	0
T23	111388	0	0	0
T24	1266	0	0	0
T25	851	0	0	0
T33	0	5043	0	0
T36	789348	0	0	0
T37	787847	0	0	0
T38	276286	0	0	0
T47	0	2961	0	0
T48	0	29285	0	0
T91	0	3480	0	0
T92	0	4964	0	0
T93	0	1884	0	0
T94	0	4076	0	0
T95	0	1711	0	0
T96	0	6015	0	0