Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59048377	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

19479187

1

T1

115

T2

163

T3

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	74085942	1			T1	162		T2	4320		T3	809
values[0x0]	2107370	1			T1	68		T2	118		T3	27
values[0x1]	2334252	1			T1	58		T2	101		T3	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41052139	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37475425

1

T1

146

T2

1590

T3

304

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	293645	1			T2	23		T3	4		T4	211
valid_sources[0x01]	283469	1			T2	16		T3	1		T4	228
valid_sources[0x02]	293992	1			T2	19		T3	4		T4	224
valid_sources[0x03]	270975	1			T2	26		T3	4		T4	226
valid_sources[0x04]	285876	1			T2	15		T3	5		T4	256
valid_sources[0x05]	315439	1			T2	22		T3	5		T4	249
valid_sources[0x06]	311786	1			T1	2		T2	21		T3	2
valid_sources[0x07]	271368	1			T2	20		T3	4		T4	250
valid_sources[0x08]	285843	1			T2	19		T3	2		T4	233
valid_sources[0x09]	305639	1			T2	19		T3	4		T4	218
valid_sources[0x0a]	306150	1			T2	19		T3	3		T4	193
valid_sources[0x0b]	263213	1			T2	25		T3	7		T4	235
valid_sources[0x0c]	305709	1			T2	18		T3	3		T4	219
valid_sources[0x0d]	322954	1			T2	15		T4	219		T5	1892
valid_sources[0x0e]	278530	1			T2	16		T3	7		T4	223
valid_sources[0x0f]	282851	1			T1	7		T2	13		T3	2
valid_sources[0x10]	281886	1			T2	9		T3	1		T4	239
valid_sources[0x11]	325564	1			T1	1		T2	14		T3	3
valid_sources[0x12]	310989	1			T2	32		T3	7		T4	235
valid_sources[0x13]	290070	1			T2	26		T3	4		T4	244
valid_sources[0x14]	336838	1			T2	26		T3	4		T4	231
valid_sources[0x15]	294630	1			T1	3		T2	15		T3	2
valid_sources[0x16]	279282	1			T2	24		T3	3		T4	240
valid_sources[0x17]	261647	1			T2	29		T3	1		T4	222
valid_sources[0x18]	282877	1			T2	21		T3	3		T4	211
valid_sources[0x19]	292596	1			T2	21		T3	3		T4	215
valid_sources[0x1a]	289561	1			T2	22		T3	3		T4	246
valid_sources[0x1b]	387889	1			T2	12		T3	2		T4	209
valid_sources[0x1c]	275721	1			T2	13		T3	3		T4	200
valid_sources[0x1d]	281566	1			T2	11		T3	2		T4	187
valid_sources[0x1e]	306301	1			T2	15		T3	3		T4	234
valid_sources[0x1f]	301840	1			T2	22		T3	2		T4	250
valid_sources[0x20]	305686	1			T1	1		T2	21		T3	2
valid_sources[0x21]	290852	1			T2	10		T3	1		T4	217
valid_sources[0x22]	321911	1			T1	2		T2	18		T3	5
valid_sources[0x23]	294258	1			T2	28		T3	4		T4	218
valid_sources[0x24]	292519	1			T1	11		T2	18		T3	12
valid_sources[0x25]	287718	1			T2	14		T3	4		T4	218
valid_sources[0x26]	324093	1			T2	11		T3	2		T4	248
valid_sources[0x27]	286202	1			T1	1		T2	7		T3	4
valid_sources[0x28]	299300	1			T1	1		T2	14		T3	5
valid_sources[0x29]	287328	1			T2	21		T3	1		T4	231
valid_sources[0x2a]	363414	1			T2	17		T3	2		T4	212
valid_sources[0x2b]	304347	1			T2	14		T3	1		T4	212
valid_sources[0x2c]	285639	1			T1	1		T2	28		T3	2
valid_sources[0x2d]	279924	1			T2	21		T3	3		T4	230
valid_sources[0x2e]	279365	1			T2	17		T3	1		T4	225
valid_sources[0x2f]	377974	1			T2	8		T3	4		T4	217
valid_sources[0x30]	304359	1			T2	12		T3	4		T4	230
valid_sources[0x31]	291828	1			T1	1		T2	11		T3	1
valid_sources[0x32]	301394	1			T2	7		T3	1		T4	213
valid_sources[0x33]	287297	1			T1	1		T2	6		T3	2
valid_sources[0x34]	294480	1			T2	18		T3	2		T4	225
valid_sources[0x35]	384085	1			T2	26		T3	4		T4	229
valid_sources[0x36]	301928	1			T2	11		T3	1		T4	212
valid_sources[0x37]	294861	1			T2	21		T3	2		T4	230
valid_sources[0x38]	287700	1			T2	12		T3	2		T4	225
valid_sources[0x39]	305211	1			T1	6		T2	29		T3	2
valid_sources[0x3a]	284469	1			T2	13		T3	4		T4	216
valid_sources[0x3b]	316819	1			T2	22		T3	2		T4	239
valid_sources[0x3c]	287486	1			T1	1		T2	19		T3	2
valid_sources[0x3d]	308907	1			T2	24		T3	6		T4	204
valid_sources[0x3e]	286895	1			T2	8		T3	5		T4	232
valid_sources[0x3f]	304698	1			T1	1		T2	24		T3	6
valid_sources[0x40]	324045	1			T2	4		T3	4		T4	223
valid_sources[0x41]	288473	1			T2	13		T3	9		T4	234
valid_sources[0x42]	461827	1			T2	32		T3	4		T4	221
valid_sources[0x43]	289477	1			T2	22		T3	6		T4	254
valid_sources[0x44]	306696	1			T2	10		T3	1		T4	216
valid_sources[0x45]	305407	1			T2	20		T3	4		T4	214
valid_sources[0x46]	285678	1			T1	4		T2	15		T3	2
valid_sources[0x47]	295747	1			T1	1		T2	25		T3	3
valid_sources[0x48]	318718	1			T1	6		T2	12		T3	7
valid_sources[0x49]	306840	1			T2	42		T3	4		T4	228
valid_sources[0x4a]	297996	1			T2	9		T3	5		T4	223
valid_sources[0x4b]	295433	1			T2	6		T3	5		T4	219
valid_sources[0x4c]	322067	1			T2	15		T3	5		T4	225
valid_sources[0x4d]	296285	1			T1	6		T2	26		T3	3
valid_sources[0x4e]	261203	1			T1	1		T2	10		T3	4
valid_sources[0x4f]	288929	1			T2	31		T3	6		T4	230
valid_sources[0x50]	289438	1			T1	2		T2	18		T3	3
valid_sources[0x51]	266962	1			T2	20		T3	3		T4	229
valid_sources[0x52]	304167	1			T2	18		T3	1		T4	232
valid_sources[0x53]	264059	1			T2	5		T3	4		T4	211
valid_sources[0x54]	314048	1			T2	14		T3	5		T4	226
valid_sources[0x55]	279336	1			T1	4		T2	12		T3	1
valid_sources[0x56]	297800	1			T1	1		T2	12		T3	4
valid_sources[0x57]	466314	1			T2	22		T3	2		T4	210
valid_sources[0x58]	288361	1			T2	20		T3	2		T4	206
valid_sources[0x59]	288399	1			T1	7		T2	13		T3	3
valid_sources[0x5a]	298609	1			T2	23		T3	2		T4	201
valid_sources[0x5b]	304045	1			T2	5		T3	2		T4	207
valid_sources[0x5c]	313258	1			T1	1		T2	31		T3	7
valid_sources[0x5d]	283092	1			T1	3		T2	28		T3	4
valid_sources[0x5e]	383529	1			T2	10		T3	3		T4	214
valid_sources[0x5f]	280487	1			T1	9		T2	14		T3	6
valid_sources[0x60]	294106	1			T2	33		T4	217		T5	2078
valid_sources[0x61]	283944	1			T2	15		T3	7		T4	252
valid_sources[0x62]	299519	1			T2	20		T3	5		T4	215
valid_sources[0x63]	295889	1			T2	23		T3	2		T4	228
valid_sources[0x64]	285111	1			T1	1		T2	8		T3	5
valid_sources[0x65]	281480	1			T1	1		T2	22		T3	1
valid_sources[0x66]	389116	1			T2	24		T3	7		T4	248
valid_sources[0x67]	325998	1			T1	5		T2	24		T3	1
valid_sources[0x68]	308172	1			T2	22		T3	1		T4	230
valid_sources[0x69]	281566	1			T1	1		T2	8		T3	4
valid_sources[0x6a]	296710	1			T2	34		T3	4		T4	239
valid_sources[0x6b]	362540	1			T1	1		T2	11		T3	1
valid_sources[0x6c]	303146	1			T1	2		T2	14		T3	7
valid_sources[0x6d]	314940	1			T2	29		T3	3		T4	209
valid_sources[0x6e]	294979	1			T2	21		T3	4		T4	240
valid_sources[0x6f]	290260	1			T1	2		T2	18		T3	2
valid_sources[0x70]	309390	1			T2	9		T3	1		T4	244
valid_sources[0x71]	283882	1			T2	21		T3	4		T4	219
valid_sources[0x72]	292627	1			T2	20		T4	227		T5	1959
valid_sources[0x73]	317494	1			T1	7		T2	14		T3	1
valid_sources[0x74]	337563	1			T2	11		T3	4		T4	245
valid_sources[0x75]	267543	1			T2	25		T3	3		T4	222
valid_sources[0x76]	288122	1			T2	23		T3	5		T4	227
valid_sources[0x77]	380342	1			T1	1		T2	15		T3	5
valid_sources[0x78]	283121	1			T2	15		T3	3		T4	223
valid_sources[0x79]	318982	1			T2	10		T4	249		T5	1788
valid_sources[0x7a]	287240	1			T2	30		T3	11		T4	223
valid_sources[0x7b]	360609	1			T2	15		T3	6		T4	203
valid_sources[0x7c]	360214	1			T2	21		T3	8		T4	265
valid_sources[0x7d]	398301	1			T1	1		T2	19		T4	217
valid_sources[0x7e]	299495	1			T2	31		T3	4		T4	223
valid_sources[0x7f]	281091	1			T1	1		T2	15		T3	4
valid_sources[0x80]	298632	1			T2	23		T3	2		T4	232

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15699781

1

T1

66

T2

86

T3

8

values[0x0]

all_enables

biggest_size

1914190

1

T1

30

T2

51

T3

10

values[0x1]

all_enables

biggest_size

1865216

1

T1

19

T2

26

T3

9