Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6087876	0	0
ctrl_rd_A	2147483647	107107	0	0
intr_enable_rd_A	2147483647	96799	0	0
ovrd_rd_A	2147483647	107510	0	0
timeout_ctrl_rd_A	2147483647	106926	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6087876	0	0
T5	201789	75633	0	0
T6	295417	0	0	0
T7	485850	0	0	0
T8	1305	0	0	0
T9	11158	0	0	0
T10	46386	0	0	0
T11	438629	0	0	0
T19	0	117380	0	0
T20	0	125472	0	0
T21	635554	0	0	0
T23	519218	0	0	0
T26	925747	0	0	0
T32	0	38792	0	0
T33	0	88508	0	0
T34	0	35203	0	0
T35	0	121741	0	0
T36	0	288687	0	0
T37	0	251715	0	0
T38	0	109625	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	107107	0	0
T32	110334	1610	0	0
T33	262551	0	0	0
T37	0	28156	0	0
T47	0	3771	0	0
T62	458315	0	0	0
T85	0	16743	0	0
T86	0	5074	0	0
T87	0	2392	0	0
T88	0	8777	0	0
T89	0	4829	0	0
T90	0	4661	0	0
T91	0	7032	0	0
T92	504081	0	0	0
T93	116346	0	0	0
T94	166737	0	0	0
T95	12095	0	0	0
T96	92392	0	0	0
T97	104555	0	0	0
T98	102780	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	96799	0	0
T32	110334	1267	0	0
T33	262551	0	0	0
T37	0	25203	0	0
T62	458315	0	0	0
T85	0	15080	0	0
T86	0	4495	0	0
T87	0	1997	0	0
T88	0	7785	0	0
T89	0	4334	0	0
T92	504081	0	0	0
T93	116346	0	0	0
T94	166737	0	0	0
T95	12095	0	0	0
T96	92392	0	0	0
T97	104555	0	0	0
T98	102780	0	0	0
T99	0	3	0	0
T100	0	68	0	0
T101	0	14	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	107510	0	0
T32	110334	1559	0	0
T33	262551	0	0	0
T37	0	28276	0	0
T47	0	3799	0	0
T62	458315	0	0	0
T85	0	17320	0	0
T86	0	4972	0	0
T87	0	2349	0	0
T88	0	8159	0	0
T89	0	5089	0	0
T90	0	4697	0	0
T91	0	7469	0	0
T92	504081	0	0	0
T93	116346	0	0	0
T94	166737	0	0	0
T95	12095	0	0	0
T96	92392	0	0	0
T97	104555	0	0	0
T98	102780	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	106926	0	0
T32	110334	1484	0	0
T33	262551	0	0	0
T37	0	27870	0	0
T47	0	3899	0	0
T62	458315	0	0	0
T85	0	16688	0	0
T86	0	5372	0	0
T87	0	2442	0	0
T88	0	8632	0	0
T89	0	4998	0	0
T90	0	4778	0	0
T91	0	7480	0	0
T92	504081	0	0	0
T93	116346	0	0	0
T94	166737	0	0	0
T95	12095	0	0	0
T96	92392	0	0	0
T97	104555	0	0	0
T98	102780	0	0	0