Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1118384 |
710602 |
0 |
0 |
T2 |
1202432 |
860777 |
0 |
0 |
T3 |
523020 |
212882 |
0 |
0 |
T4 |
247698 |
12799 |
0 |
0 |
T5 |
604652 |
634645 |
0 |
0 |
T6 |
322778 |
971944 |
0 |
0 |
T7 |
1441900 |
688154 |
0 |
0 |
T8 |
468950 |
1401155 |
0 |
0 |
T9 |
296856 |
141419 |
0 |
0 |
T10 |
277946 |
1014149 |
0 |
0 |
T11 |
0 |
71070 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1118384 |
1118248 |
0 |
0 |
T2 |
1202432 |
1202418 |
0 |
0 |
T3 |
523020 |
522892 |
0 |
0 |
T4 |
247698 |
247572 |
0 |
0 |
T5 |
604652 |
604630 |
0 |
0 |
T6 |
322778 |
322756 |
0 |
0 |
T7 |
1441900 |
1441882 |
0 |
0 |
T8 |
468950 |
468932 |
0 |
0 |
T9 |
296856 |
296842 |
0 |
0 |
T10 |
277946 |
277946 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1118384 |
1118248 |
0 |
0 |
T2 |
1202432 |
1202418 |
0 |
0 |
T3 |
523020 |
522892 |
0 |
0 |
T4 |
247698 |
247572 |
0 |
0 |
T5 |
604652 |
604630 |
0 |
0 |
T6 |
322778 |
322756 |
0 |
0 |
T7 |
1441900 |
1441882 |
0 |
0 |
T8 |
468950 |
468932 |
0 |
0 |
T9 |
296856 |
296842 |
0 |
0 |
T10 |
277946 |
277946 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1118384 |
1118248 |
0 |
0 |
T2 |
1202432 |
1202418 |
0 |
0 |
T3 |
523020 |
522892 |
0 |
0 |
T4 |
247698 |
247572 |
0 |
0 |
T5 |
604652 |
604630 |
0 |
0 |
T6 |
322778 |
322756 |
0 |
0 |
T7 |
1441900 |
1441882 |
0 |
0 |
T8 |
468950 |
468932 |
0 |
0 |
T9 |
296856 |
296842 |
0 |
0 |
T10 |
277946 |
277946 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1118384 |
710602 |
0 |
0 |
T2 |
1202432 |
860777 |
0 |
0 |
T3 |
523020 |
212882 |
0 |
0 |
T4 |
247698 |
12799 |
0 |
0 |
T5 |
604652 |
634645 |
0 |
0 |
T6 |
322778 |
971944 |
0 |
0 |
T7 |
1441900 |
688154 |
0 |
0 |
T8 |
468950 |
1401155 |
0 |
0 |
T9 |
296856 |
141419 |
0 |
0 |
T10 |
277946 |
1014149 |
0 |
0 |
T11 |
0 |
71070 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T4 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1666622528 |
0 |
0 |
T1 |
559192 |
269768 |
0 |
0 |
T2 |
601216 |
589255 |
0 |
0 |
T3 |
261510 |
0 |
0 |
0 |
T4 |
123849 |
11962 |
0 |
0 |
T5 |
302326 |
121978 |
0 |
0 |
T6 |
161389 |
598261 |
0 |
0 |
T7 |
720950 |
688154 |
0 |
0 |
T8 |
234475 |
556509 |
0 |
0 |
T9 |
148428 |
141139 |
0 |
0 |
T10 |
138973 |
899815 |
0 |
0 |
T11 |
0 |
66358 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
559192 |
559124 |
0 |
0 |
T2 |
601216 |
601209 |
0 |
0 |
T3 |
261510 |
261446 |
0 |
0 |
T4 |
123849 |
123786 |
0 |
0 |
T5 |
302326 |
302315 |
0 |
0 |
T6 |
161389 |
161378 |
0 |
0 |
T7 |
720950 |
720941 |
0 |
0 |
T8 |
234475 |
234466 |
0 |
0 |
T9 |
148428 |
148421 |
0 |
0 |
T10 |
138973 |
138973 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
559192 |
559124 |
0 |
0 |
T2 |
601216 |
601209 |
0 |
0 |
T3 |
261510 |
261446 |
0 |
0 |
T4 |
123849 |
123786 |
0 |
0 |
T5 |
302326 |
302315 |
0 |
0 |
T6 |
161389 |
161378 |
0 |
0 |
T7 |
720950 |
720941 |
0 |
0 |
T8 |
234475 |
234466 |
0 |
0 |
T9 |
148428 |
148421 |
0 |
0 |
T10 |
138973 |
138973 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
559192 |
559124 |
0 |
0 |
T2 |
601216 |
601209 |
0 |
0 |
T3 |
261510 |
261446 |
0 |
0 |
T4 |
123849 |
123786 |
0 |
0 |
T5 |
302326 |
302315 |
0 |
0 |
T6 |
161389 |
161378 |
0 |
0 |
T7 |
720950 |
720941 |
0 |
0 |
T8 |
234475 |
234466 |
0 |
0 |
T9 |
148428 |
148421 |
0 |
0 |
T10 |
138973 |
138973 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1666622528 |
0 |
0 |
T1 |
559192 |
269768 |
0 |
0 |
T2 |
601216 |
589255 |
0 |
0 |
T3 |
261510 |
0 |
0 |
0 |
T4 |
123849 |
11962 |
0 |
0 |
T5 |
302326 |
121978 |
0 |
0 |
T6 |
161389 |
598261 |
0 |
0 |
T7 |
720950 |
688154 |
0 |
0 |
T8 |
234475 |
556509 |
0 |
0 |
T9 |
148428 |
141139 |
0 |
0 |
T10 |
138973 |
899815 |
0 |
0 |
T11 |
0 |
66358 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T12,T13 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T5,T12,T13 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
656991014 |
0 |
0 |
T1 |
559192 |
440834 |
0 |
0 |
T2 |
601216 |
271522 |
0 |
0 |
T3 |
261510 |
212882 |
0 |
0 |
T4 |
123849 |
837 |
0 |
0 |
T5 |
302326 |
512667 |
0 |
0 |
T6 |
161389 |
373683 |
0 |
0 |
T7 |
720950 |
0 |
0 |
0 |
T8 |
234475 |
844646 |
0 |
0 |
T9 |
148428 |
280 |
0 |
0 |
T10 |
138973 |
114334 |
0 |
0 |
T11 |
0 |
4712 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
559192 |
559124 |
0 |
0 |
T2 |
601216 |
601209 |
0 |
0 |
T3 |
261510 |
261446 |
0 |
0 |
T4 |
123849 |
123786 |
0 |
0 |
T5 |
302326 |
302315 |
0 |
0 |
T6 |
161389 |
161378 |
0 |
0 |
T7 |
720950 |
720941 |
0 |
0 |
T8 |
234475 |
234466 |
0 |
0 |
T9 |
148428 |
148421 |
0 |
0 |
T10 |
138973 |
138973 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
559192 |
559124 |
0 |
0 |
T2 |
601216 |
601209 |
0 |
0 |
T3 |
261510 |
261446 |
0 |
0 |
T4 |
123849 |
123786 |
0 |
0 |
T5 |
302326 |
302315 |
0 |
0 |
T6 |
161389 |
161378 |
0 |
0 |
T7 |
720950 |
720941 |
0 |
0 |
T8 |
234475 |
234466 |
0 |
0 |
T9 |
148428 |
148421 |
0 |
0 |
T10 |
138973 |
138973 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
559192 |
559124 |
0 |
0 |
T2 |
601216 |
601209 |
0 |
0 |
T3 |
261510 |
261446 |
0 |
0 |
T4 |
123849 |
123786 |
0 |
0 |
T5 |
302326 |
302315 |
0 |
0 |
T6 |
161389 |
161378 |
0 |
0 |
T7 |
720950 |
720941 |
0 |
0 |
T8 |
234475 |
234466 |
0 |
0 |
T9 |
148428 |
148421 |
0 |
0 |
T10 |
138973 |
138973 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
656991014 |
0 |
0 |
T1 |
559192 |
440834 |
0 |
0 |
T2 |
601216 |
271522 |
0 |
0 |
T3 |
261510 |
212882 |
0 |
0 |
T4 |
123849 |
837 |
0 |
0 |
T5 |
302326 |
512667 |
0 |
0 |
T6 |
161389 |
373683 |
0 |
0 |
T7 |
720950 |
0 |
0 |
0 |
T8 |
234475 |
844646 |
0 |
0 |
T9 |
148428 |
280 |
0 |
0 |
T10 |
138973 |
114334 |
0 |
0 |
T11 |
0 |
4712 |
0 |
0 |