Unified Coverage Report :: Module :: prim_subreg_arb

Module : prim_subreg_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.76	83.33	97.96			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_intr_state_tx_watermark.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_intr_state_rx_watermark.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_intr_state_tx_empty.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_fifo_ctrl_rxilvl.wr_en_data_arb	95.24	100.00	85.71			100.00
tb.dut.u_reg.u_fifo_ctrl_txilvl.wr_en_data_arb	95.24	100.00	85.71			100.00
tb.dut.u_reg.u_intr_state_tx_done.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_state_rx_frame_err.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_state_rx_break_err.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_state_rx_timeout.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_state_rx_parity_err.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_enable_tx_watermark.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_watermark.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_tx_done.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_frame_err.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_break_err.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_timeout.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_parity_err.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_tx_empty.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_tx.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_rx.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_nf.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_slpbk.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_parity_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_parity_odd.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_rxblvl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ctrl_nco.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_wdata.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ovrd_txen.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ovrd_txval.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_intr_state_tx_watermark.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_intr_state_rx_watermark.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_intr_state_tx_empty.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	1	50.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	0	1
44	1	1
51		unreachable
52		unreachable
53		unreachable

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_tx_done.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_frame_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_break_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_timeout.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_parity_err.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=8,SwAccess=2,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=24,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_watermark.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_watermark.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_done.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_frame_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_break_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_timeout.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_parity_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_empty.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_tx.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_rx.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_nf.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_slpbk.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_parity_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_parity_odd.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_rxblvl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ctrl_nco.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_wdata.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb

SCORE	LINE
95.24	100.00

tb.dut.u_reg.u_fifo_ctrl_rxilvl.wr_en_data_arb

SCORE	LINE
95.24	100.00

tb.dut.u_reg.u_fifo_ctrl_txilvl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ovrd_txen.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ovrd_txval.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
95.24	85.71

tb.dut.u_reg.u_fifo_ctrl_rxilvl.wr_en_data_arb

SCORE	COND
95.24	85.71

tb.dut.u_reg.u_fifo_ctrl_txilvl.wr_en_data_arb

	Total	Covered	Percent
Conditions	7	6	85.71
Logical	7	6	85.71
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_tx_done.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_frame_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_break_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_timeout.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_parity_err.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_watermark.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_watermark.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_done.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_frame_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_break_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_timeout.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_parity_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_tx_empty.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_tx.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_rx.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_nf.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_slpbk.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_parity_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_parity_odd.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ovrd_txen.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ovrd_txval.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_nco.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ctrl_rxblvl.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=2,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_wdata.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=24,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_subreg_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3