Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	9496898	0	0
ctrl_rd_A	2147483647	179045	0	0
intr_enable_rd_A	2147483647	160809	0	0
ovrd_rd_A	2147483647	177860	0	0
timeout_ctrl_rd_A	2147483647	177208	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9496898	0	0
T5	302326	93735	0	0
T6	161389	39950	0	0
T7	720950	0	0	0
T8	234475	0	0	0
T9	148428	0	0	0
T10	138973	0	0	0
T11	482633	0	0	0
T13	0	121341	0	0
T14	178718	0	0	0
T18	375291	0	0	0
T26	0	74261	0	0
T27	0	236819	0	0
T28	0	38665	0	0
T29	0	95327	0	0
T30	0	140151	0	0
T31	0	127205	0	0
T32	0	276139	0	0
T33	601417	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	179045	0	0
T5	302326	4656	0	0
T6	161389	0	0	0
T7	720950	0	0	0
T8	234475	0	0	0
T9	148428	0	0	0
T10	138973	0	0	0
T11	482633	0	0	0
T13	0	13113	0	0
T14	178718	0	0	0
T18	375291	0	0	0
T26	0	3600	0	0
T31	0	13870	0	0
T32	0	12545	0	0
T33	601417	0	0	0
T49	0	14639	0	0
T88	0	4862	0	0
T97	0	7985	0	0
T98	0	3787	0	0
T99	0	8966	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	160809	0	0
T5	302326	4523	0	0
T6	161389	0	0	0
T7	720950	0	0	0
T8	234475	0	0	0
T9	148428	0	0	0
T10	138973	0	0	0
T11	482633	0	0	0
T13	0	12219	0	0
T14	178718	0	0	0
T18	375291	0	0	0
T26	0	3598	0	0
T31	0	12534	0	0
T32	0	11308	0	0
T33	601417	0	0	0
T88	0	4404	0	0
T97	0	7280	0	0
T100	0	18	0	0
T101	0	14	0	0
T102	0	12	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	177860	0	0
T5	302326	5032	0	0
T6	161389	0	0	0
T7	720950	0	0	0
T8	234475	0	0	0
T9	148428	0	0	0
T10	138973	0	0	0
T11	482633	0	0	0
T13	0	14129	0	0
T14	178718	0	0	0
T18	375291	0	0	0
T26	0	3739	0	0
T31	0	14123	0	0
T32	0	11821	0	0
T33	601417	0	0	0
T49	0	14703	0	0
T88	0	5129	0	0
T97	0	7418	0	0
T98	0	3869	0	0
T99	0	8323	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	177208	0	0
T5	302326	5154	0	0
T6	161389	0	0	0
T7	720950	0	0	0
T8	234475	0	0	0
T9	148428	0	0	0
T10	138973	0	0	0
T11	482633	0	0	0
T13	0	14189	0	0
T14	178718	0	0	0
T18	375291	0	0	0
T26	0	3546	0	0
T31	0	13853	0	0
T32	0	12096	0	0
T33	601417	0	0	0
T49	0	15091	0	0
T88	0	5092	0	0
T97	0	7503	0	0
T98	0	3669	0	0
T99	0	8476	0	0