Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	68505402	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24311344

1

T1

22

T2

174

T3

122

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	85663797	1			T1	14980		T2	4691		T3	1255
values[0x0]	3384003	1			T1	27		T2	150		T3	48
values[0x1]	3768946	1			T1	18		T2	145		T3	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47489092	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

45327654

1

T1

4933

T2

1746

T3

521

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	340954	1			T1	48		T2	18		T3	6
valid_sources[0x01]	344979	1			T1	83		T2	19		T3	3
valid_sources[0x02]	391746	1			T1	53		T2	30		T3	6
valid_sources[0x03]	347600	1			T1	51		T2	12		T3	8
valid_sources[0x04]	335737	1			T1	85		T2	29		T3	5
valid_sources[0x05]	347962	1			T1	72		T2	16		T3	4
valid_sources[0x06]	348544	1			T1	55		T2	18		T4	38
valid_sources[0x07]	390219	1			T1	74		T2	19		T3	7
valid_sources[0x08]	384968	1			T1	61		T2	15		T3	9
valid_sources[0x09]	381882	1			T1	38		T2	35		T3	6
valid_sources[0x0a]	335012	1			T1	57		T2	30		T3	8
valid_sources[0x0b]	342788	1			T1	73		T2	8		T3	3
valid_sources[0x0c]	338346	1			T1	59		T2	12		T3	6
valid_sources[0x0d]	338815	1			T1	64		T2	11		T3	2
valid_sources[0x0e]	349949	1			T1	68		T2	26		T3	3
valid_sources[0x0f]	334840	1			T1	71		T2	14		T3	3
valid_sources[0x10]	368182	1			T1	48		T2	17		T3	2
valid_sources[0x11]	347086	1			T1	61		T2	17		T3	7
valid_sources[0x12]	345833	1			T1	58		T2	10		T3	2
valid_sources[0x13]	352003	1			T1	49		T2	22		T3	11
valid_sources[0x14]	344369	1			T1	69		T2	14		T3	9
valid_sources[0x15]	377734	1			T1	39		T2	20		T3	3
valid_sources[0x16]	357287	1			T1	71		T2	16		T3	6
valid_sources[0x17]	355620	1			T1	61		T2	23		T3	11
valid_sources[0x18]	337657	1			T1	53		T2	7		T3	2
valid_sources[0x19]	349975	1			T1	72		T2	14		T3	8
valid_sources[0x1a]	340110	1			T1	51		T2	17		T3	5
valid_sources[0x1b]	334821	1			T1	52		T2	35		T3	6
valid_sources[0x1c]	340267	1			T1	73		T2	34		T3	11
valid_sources[0x1d]	374628	1			T1	71		T2	29		T3	12
valid_sources[0x1e]	361214	1			T1	49		T2	16		T3	6
valid_sources[0x1f]	361450	1			T1	72		T2	17		T3	7
valid_sources[0x20]	348984	1			T1	58		T2	11		T3	1
valid_sources[0x21]	348644	1			T1	50		T2	20		T3	3
valid_sources[0x22]	332592	1			T1	68		T2	30		T3	4
valid_sources[0x23]	353962	1			T1	54		T2	11		T3	8
valid_sources[0x24]	356416	1			T1	63		T2	11		T3	6
valid_sources[0x25]	513260	1			T1	47		T2	21		T3	8
valid_sources[0x26]	356492	1			T1	69		T2	20		T3	4
valid_sources[0x27]	347413	1			T1	52		T2	11		T3	4
valid_sources[0x28]	350058	1			T1	62		T2	28		T3	4
valid_sources[0x29]	341767	1			T1	59		T2	11		T3	9
valid_sources[0x2a]	339930	1			T1	75		T2	15		T3	12
valid_sources[0x2b]	352103	1			T1	72		T2	20		T3	5
valid_sources[0x2c]	350884	1			T1	67		T2	17		T3	9
valid_sources[0x2d]	344669	1			T1	75		T2	22		T3	3
valid_sources[0x2e]	356338	1			T1	75		T2	18		T3	4
valid_sources[0x2f]	390000	1			T1	45		T2	12		T3	5
valid_sources[0x30]	333893	1			T1	72		T2	16		T3	6
valid_sources[0x31]	366596	1			T1	54		T2	19		T3	5
valid_sources[0x32]	345034	1			T1	52		T2	25		T3	7
valid_sources[0x33]	361128	1			T1	74		T2	21		T3	3
valid_sources[0x34]	378943	1			T1	33		T2	35		T3	3
valid_sources[0x35]	391696	1			T1	51		T2	11		T3	13
valid_sources[0x36]	344191	1			T1	56		T2	19		T3	11
valid_sources[0x37]	340895	1			T1	49		T2	20		T3	5
valid_sources[0x38]	334167	1			T1	45		T2	22		T3	6
valid_sources[0x39]	353185	1			T1	85		T2	32		T3	6
valid_sources[0x3a]	341141	1			T1	55		T2	26		T3	4
valid_sources[0x3b]	346720	1			T1	38		T2	23		T3	6
valid_sources[0x3c]	346822	1			T1	53		T2	35		T3	7
valid_sources[0x3d]	332620	1			T1	54		T2	6		T3	3
valid_sources[0x3e]	421260	1			T1	56		T2	28		T3	8
valid_sources[0x3f]	339518	1			T1	44		T2	22		T3	10
valid_sources[0x40]	345984	1			T1	53		T2	17		T3	7
valid_sources[0x41]	356532	1			T1	46		T2	32		T3	7
valid_sources[0x42]	359513	1			T1	75		T2	21		T3	8
valid_sources[0x43]	343302	1			T1	47		T2	10		T3	6
valid_sources[0x44]	343131	1			T1	55		T2	12		T3	10
valid_sources[0x45]	357740	1			T1	72		T2	23		T3	6
valid_sources[0x46]	341875	1			T1	74		T2	20		T3	4
valid_sources[0x47]	337718	1			T1	53		T2	23		T3	6
valid_sources[0x48]	356714	1			T1	51		T2	15		T3	5
valid_sources[0x49]	352938	1			T1	72		T2	22		T3	4
valid_sources[0x4a]	344790	1			T1	51		T2	21		T3	11
valid_sources[0x4b]	356671	1			T1	56		T2	17		T3	4
valid_sources[0x4c]	349071	1			T1	69		T2	18		T3	3
valid_sources[0x4d]	336100	1			T1	76		T2	20		T3	10
valid_sources[0x4e]	344858	1			T1	64		T2	36		T3	3
valid_sources[0x4f]	383188	1			T1	58		T2	18		T3	4
valid_sources[0x50]	340536	1			T1	35		T2	17		T3	6
valid_sources[0x51]	362868	1			T1	57		T2	17		T3	5
valid_sources[0x52]	355737	1			T1	57		T2	25		T3	5
valid_sources[0x53]	334555	1			T1	57		T2	38		T3	8
valid_sources[0x54]	354835	1			T1	48		T2	21		T3	6
valid_sources[0x55]	364138	1			T1	82		T2	26		T3	4
valid_sources[0x56]	351026	1			T1	55		T2	19		T3	3
valid_sources[0x57]	361947	1			T1	41		T2	13		T3	3
valid_sources[0x58]	329613	1			T1	52		T2	25		T3	4
valid_sources[0x59]	460924	1			T1	65		T2	14		T3	5
valid_sources[0x5a]	361943	1			T1	64		T2	16		T3	8
valid_sources[0x5b]	376555	1			T1	65		T2	12		T3	5
valid_sources[0x5c]	351135	1			T1	46		T2	14		T3	3
valid_sources[0x5d]	359099	1			T1	51		T2	25		T3	5
valid_sources[0x5e]	378771	1			T1	65		T2	20		T3	4
valid_sources[0x5f]	419524	1			T1	84		T2	16		T3	4
valid_sources[0x60]	357222	1			T1	65		T2	17		T3	5
valid_sources[0x61]	328704	1			T1	39		T2	14		T3	8
valid_sources[0x62]	345466	1			T1	42		T2	25		T3	5
valid_sources[0x63]	493191	1			T1	46		T2	25		T3	5
valid_sources[0x64]	337849	1			T1	56		T2	20		T3	7
valid_sources[0x65]	353601	1			T1	66		T2	21		T3	8
valid_sources[0x66]	342599	1			T1	50		T2	12		T3	4
valid_sources[0x67]	353585	1			T1	62		T2	15		T3	8
valid_sources[0x68]	332208	1			T1	31		T2	6		T3	1
valid_sources[0x69]	355595	1			T1	43		T2	28		T3	3
valid_sources[0x6a]	360007	1			T1	45		T2	24		T3	4
valid_sources[0x6b]	347099	1			T1	59		T2	17		T4	43
valid_sources[0x6c]	348730	1			T1	72		T2	28		T3	5
valid_sources[0x6d]	368451	1			T1	33		T2	15		T3	7
valid_sources[0x6e]	346959	1			T1	67		T2	7		T3	11
valid_sources[0x6f]	355582	1			T1	51		T2	16		T3	2
valid_sources[0x70]	353040	1			T1	60		T2	18		T3	6
valid_sources[0x71]	363172	1			T1	56		T2	22		T3	8
valid_sources[0x72]	358776	1			T1	42		T2	16		T3	7
valid_sources[0x73]	358212	1			T1	41		T2	15		T3	5
valid_sources[0x74]	339599	1			T1	47		T2	24		T3	7
valid_sources[0x75]	352393	1			T1	48		T2	22		T3	3
valid_sources[0x76]	332612	1			T1	69		T2	33		T3	4
valid_sources[0x77]	413015	1			T1	68		T2	19		T3	2
valid_sources[0x78]	387580	1			T1	40		T2	16		T3	4
valid_sources[0x79]	367645	1			T1	78		T2	16		T3	3
valid_sources[0x7a]	343913	1			T1	42		T2	13		T3	4
valid_sources[0x7b]	357485	1			T1	48		T2	17		T3	3
valid_sources[0x7c]	349473	1			T1	56		T2	28		T3	5
valid_sources[0x7d]	354063	1			T1	61		T2	22		T3	4
valid_sources[0x7e]	384526	1			T1	45		T2	26		T3	4
valid_sources[0x7f]	352197	1			T1	50		T2	19		T3	10
valid_sources[0x80]	347627	1			T1	55		T2	16		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18053770

1

T1

7

T2

76

T3

88

values[0x0]

all_enables

biggest_size

3154792

1

T1

11

T2

59

T3

23

values[0x1]

all_enables

biggest_size

3102782

1

T1

4

T2

39

T3

11