Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	10268696	0	0
ctrl_rd_A	2147483647	220171	0	0
intr_enable_rd_A	2147483647	195638	0	0
ovrd_rd_A	2147483647	218684	0	0
timeout_ctrl_rd_A	2147483647	219568	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10268696	0	0
T12	279033	119823	0	0
T13	0	110198	0	0
T14	620568	0	0	0
T15	192195	0	0	0
T17	0	49693	0	0
T20	68783	0	0	0
T21	167831	0	0	0
T29	0	167616	0	0
T30	0	118905	0	0
T31	0	29357	0	0
T32	0	238706	0	0
T33	0	82174	0	0
T34	0	135556	0	0
T35	0	141538	0	0
T36	242599	0	0	0
T37	328084	0	0	0
T38	115722	0	0	0
T39	245057	0	0	0
T40	168489	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	220171	0	0
T17	203134	6089	0	0
T29	410501	0	0	0
T30	0	14365	0	0
T32	0	12472	0	0
T50	256787	0	0	0
T99	0	15444	0	0
T104	0	13109	0	0
T105	0	15391	0	0
T106	0	2970	0	0
T107	0	7235	0	0
T108	0	7966	0	0
T109	0	8977	0	0
T110	176969	0	0	0
T111	720321	0	0	0
T112	471551	0	0	0
T113	106657	0	0	0
T114	722	0	0	0
T115	140332	0	0	0
T116	293395	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	195638	0	0
T17	203134	5169	0	0
T29	410501	0	0	0
T30	0	12421	0	0
T32	0	10932	0	0
T50	256787	0	0	0
T99	0	14644	0	0
T104	0	11326	0	0
T105	0	13937	0	0
T106	0	2375	0	0
T107	0	6080	0	0
T108	0	7696	0	0
T110	176969	0	0	0
T111	720321	0	0	0
T112	471551	0	0	0
T113	106657	0	0	0
T114	722	0	0	0
T115	140332	0	0	0
T116	293395	0	0	0
T117	0	16	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	218684	0	0
T17	203134	5769	0	0
T29	410501	0	0	0
T30	0	13834	0	0
T32	0	12647	0	0
T50	256787	0	0	0
T99	0	15795	0	0
T104	0	12750	0	0
T105	0	15369	0	0
T106	0	2935	0	0
T107	0	7047	0	0
T108	0	8703	0	0
T109	0	8863	0	0
T110	176969	0	0	0
T111	720321	0	0	0
T112	471551	0	0	0
T113	106657	0	0	0
T114	722	0	0	0
T115	140332	0	0	0
T116	293395	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	219568	0	0
T17	203134	5432	0	0
T29	410501	0	0	0
T30	0	14471	0	0
T32	0	13150	0	0
T50	256787	0	0	0
T99	0	15871	0	0
T104	0	12761	0	0
T105	0	15517	0	0
T106	0	3038	0	0
T107	0	7311	0	0
T108	0	8888	0	0
T109	0	8764	0	0
T110	176969	0	0	0
T111	720321	0	0	0
T112	471551	0	0	0
T113	106657	0	0	0
T114	722	0	0	0
T115	140332	0	0	0
T116	293395	0	0	0