Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 68824327 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 23943079 1 T1 196 T2 42 T3 216869



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 85654260 1 T1 33422 T2 16471 T3 267408
values[0x0] 3366676 1 T1 172 T2 35 T3 47789
values[0x1] 3746470 1 T1 189 T2 24 T3 53695



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 47688464 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 45078942 1 T1 11418 T2 8374 T3 257083



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 341665 1 T1 199 T2 62 T3 1485
valid_sources[0x01] 369872 1 T1 127 T2 46 T3 1515
valid_sources[0x02] 339724 1 T1 106 T2 90 T3 1441
valid_sources[0x03] 355792 1 T1 242 T2 51 T3 1428
valid_sources[0x04] 339414 1 T1 201 T2 48 T3 1420
valid_sources[0x05] 359805 1 T1 120 T2 108 T3 1500
valid_sources[0x06] 352982 1 T1 75 T2 48 T3 1419
valid_sources[0x07] 351294 1 T1 156 T2 73 T3 1475
valid_sources[0x08] 353268 1 T1 151 T2 61 T3 1479
valid_sources[0x09] 352614 1 T1 168 T2 54 T3 1353
valid_sources[0x0a] 362486 1 T1 80 T2 45 T3 1431
valid_sources[0x0b] 341260 1 T1 108 T2 93 T3 1416
valid_sources[0x0c] 347676 1 T1 149 T2 52 T3 1403
valid_sources[0x0d] 361047 1 T1 140 T2 65 T3 1409
valid_sources[0x0e] 482462 1 T1 78 T2 82 T3 1364
valid_sources[0x0f] 339704 1 T1 141 T2 64 T3 1301
valid_sources[0x10] 321697 1 T1 216 T2 41 T3 1398
valid_sources[0x11] 339143 1 T1 113 T2 102 T3 1418
valid_sources[0x12] 324908 1 T1 187 T2 41 T3 1394
valid_sources[0x13] 360599 1 T1 119 T2 61 T3 1439
valid_sources[0x14] 388782 1 T1 126 T2 87 T3 1434
valid_sources[0x15] 363760 1 T1 97 T2 54 T3 1465
valid_sources[0x16] 345742 1 T1 139 T2 43 T3 1380
valid_sources[0x17] 363303 1 T1 95 T2 70 T3 1408
valid_sources[0x18] 353789 1 T1 113 T2 29 T3 1396
valid_sources[0x19] 340703 1 T1 227 T2 43 T3 1349
valid_sources[0x1a] 342678 1 T1 130 T2 67 T3 1424
valid_sources[0x1b] 413479 1 T1 58 T2 66 T3 1409
valid_sources[0x1c] 352704 1 T1 110 T2 78 T3 1518
valid_sources[0x1d] 344095 1 T1 125 T2 54 T3 1498
valid_sources[0x1e] 401921 1 T1 95 T2 50 T3 1435
valid_sources[0x1f] 330417 1 T1 146 T2 70 T3 1549
valid_sources[0x20] 378000 1 T1 145 T2 47 T3 1424
valid_sources[0x21] 338438 1 T1 150 T2 49 T3 1456
valid_sources[0x22] 325433 1 T1 109 T2 29 T3 1484
valid_sources[0x23] 335949 1 T1 156 T2 62 T3 1463
valid_sources[0x24] 353540 1 T1 309 T2 83 T3 1402
valid_sources[0x25] 367339 1 T1 124 T2 43 T3 1512
valid_sources[0x26] 421262 1 T1 80 T2 71 T3 1435
valid_sources[0x27] 325862 1 T1 111 T2 52 T3 1470
valid_sources[0x28] 361514 1 T1 61 T2 88 T3 1333
valid_sources[0x29] 354258 1 T1 115 T2 67 T3 1442
valid_sources[0x2a] 343254 1 T1 130 T2 50 T3 1443
valid_sources[0x2b] 324251 1 T1 311 T2 35 T3 1449
valid_sources[0x2c] 338698 1 T1 126 T2 68 T3 1481
valid_sources[0x2d] 368383 1 T1 208 T2 56 T3 1286
valid_sources[0x2e] 367257 1 T1 204 T2 87 T3 1464
valid_sources[0x2f] 368812 1 T1 117 T2 56 T3 1356
valid_sources[0x30] 334110 1 T1 152 T2 96 T3 1535
valid_sources[0x31] 372925 1 T1 104 T2 48 T3 1499
valid_sources[0x32] 339071 1 T1 92 T2 45 T3 1365
valid_sources[0x33] 448082 1 T1 90 T2 70 T3 1418
valid_sources[0x34] 353093 1 T1 216 T2 70 T3 1528
valid_sources[0x35] 328212 1 T1 153 T2 80 T3 1444
valid_sources[0x36] 364608 1 T1 143 T2 71 T3 1476
valid_sources[0x37] 366109 1 T1 182 T2 59 T3 1435
valid_sources[0x38] 391342 1 T1 102 T2 72 T3 1395
valid_sources[0x39] 406973 1 T1 112 T2 49 T3 1457
valid_sources[0x3a] 345984 1 T1 127 T2 56 T3 1469
valid_sources[0x3b] 343448 1 T1 99 T2 57 T3 1445
valid_sources[0x3c] 334600 1 T1 138 T2 29 T3 1386
valid_sources[0x3d] 313044 1 T1 143 T2 40 T3 1392
valid_sources[0x3e] 334383 1 T1 141 T2 53 T3 1508
valid_sources[0x3f] 347304 1 T1 185 T2 86 T3 1454
valid_sources[0x40] 320974 1 T1 112 T2 91 T3 1406
valid_sources[0x41] 375686 1 T1 167 T2 33 T3 1367
valid_sources[0x42] 355890 1 T1 198 T2 57 T3 1521
valid_sources[0x43] 373856 1 T1 169 T2 66 T3 1372
valid_sources[0x44] 364976 1 T1 163 T2 58 T3 1424
valid_sources[0x45] 362632 1 T1 81 T2 60 T3 1499
valid_sources[0x46] 391127 1 T1 46 T2 90 T3 1469
valid_sources[0x47] 343763 1 T1 145 T2 34 T3 1564
valid_sources[0x48] 347023 1 T1 135 T2 33 T3 1505
valid_sources[0x49] 380279 1 T1 143 T2 38 T3 1521
valid_sources[0x4a] 345408 1 T1 166 T2 66 T3 1365
valid_sources[0x4b] 346857 1 T1 180 T2 40 T3 1424
valid_sources[0x4c] 476481 1 T1 163 T2 65 T3 1498
valid_sources[0x4d] 326289 1 T1 184 T2 46 T3 1456
valid_sources[0x4e] 389538 1 T1 65 T2 86 T3 1508
valid_sources[0x4f] 332407 1 T1 86 T2 64 T3 1381
valid_sources[0x50] 362086 1 T1 102 T2 96 T3 1451
valid_sources[0x51] 366152 1 T1 154 T2 45 T3 1540
valid_sources[0x52] 335954 1 T1 127 T2 63 T3 1351
valid_sources[0x53] 323864 1 T1 216 T2 72 T3 1347
valid_sources[0x54] 417121 1 T1 255 T2 90 T3 1302
valid_sources[0x55] 410576 1 T1 100 T2 49 T3 1365
valid_sources[0x56] 404626 1 T1 194 T2 45 T3 1469
valid_sources[0x57] 354469 1 T1 135 T2 63 T3 1454
valid_sources[0x58] 334493 1 T1 216 T2 61 T3 1607
valid_sources[0x59] 376648 1 T1 119 T2 63 T3 1449
valid_sources[0x5a] 405384 1 T1 160 T2 44 T3 1399
valid_sources[0x5b] 406096 1 T1 140 T2 52 T3 1496
valid_sources[0x5c] 388512 1 T1 61 T2 39 T3 1422
valid_sources[0x5d] 345926 1 T1 94 T2 63 T3 1436
valid_sources[0x5e] 338051 1 T1 153 T2 52 T3 1536
valid_sources[0x5f] 362539 1 T1 93 T2 68 T3 1548
valid_sources[0x60] 398985 1 T1 175 T2 72 T3 1409
valid_sources[0x61] 355935 1 T1 42 T2 89 T3 1485
valid_sources[0x62] 390972 1 T1 80 T2 51 T3 1530
valid_sources[0x63] 383685 1 T1 189 T2 89 T3 1467
valid_sources[0x64] 382799 1 T1 158 T2 74 T3 1373
valid_sources[0x65] 357704 1 T1 140 T2 55 T3 1413
valid_sources[0x66] 339900 1 T1 98 T2 79 T3 1410
valid_sources[0x67] 353466 1 T1 145 T2 52 T3 1540
valid_sources[0x68] 392433 1 T1 172 T2 59 T3 1417
valid_sources[0x69] 388978 1 T1 137 T2 79 T3 1389
valid_sources[0x6a] 384083 1 T1 117 T2 57 T3 1507
valid_sources[0x6b] 358129 1 T1 107 T2 111 T3 1593
valid_sources[0x6c] 337088 1 T1 183 T2 63 T3 1497
valid_sources[0x6d] 340172 1 T1 139 T2 62 T3 1457
valid_sources[0x6e] 337964 1 T1 104 T2 77 T3 1372
valid_sources[0x6f] 335779 1 T1 125 T2 21 T3 1334
valid_sources[0x70] 342433 1 T1 190 T2 20 T3 1363
valid_sources[0x71] 370195 1 T1 141 T2 40 T3 1412
valid_sources[0x72] 363505 1 T1 194 T2 45 T3 1408
valid_sources[0x73] 359419 1 T1 72 T2 56 T3 1463
valid_sources[0x74] 362456 1 T1 93 T2 109 T3 1481
valid_sources[0x75] 377051 1 T1 156 T2 55 T3 1456
valid_sources[0x76] 394880 1 T1 114 T2 42 T3 1560
valid_sources[0x77] 350865 1 T1 65 T2 77 T3 1366
valid_sources[0x78] 341312 1 T1 73 T2 39 T3 1392
valid_sources[0x79] 369242 1 T1 69 T2 52 T3 1470
valid_sources[0x7a] 458961 1 T1 157 T2 76 T3 1453
valid_sources[0x7b] 353961 1 T1 119 T2 47 T3 1349
valid_sources[0x7c] 343883 1 T1 125 T2 48 T3 1424
valid_sources[0x7d] 463731 1 T1 114 T2 65 T3 1510
valid_sources[0x7e] 368096 1 T1 87 T2 80 T3 1431
valid_sources[0x7f] 370060 1 T1 198 T2 66 T3 1449
valid_sources[0x80] 396947 1 T1 97 T2 41 T3 1435



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 17722783 1 T1 79 T3 123251 T4 7
values[0x0] all_enables biggest_size 3137393 1 T1 74 T2 27 T3 46883
values[0x1] all_enables biggest_size 3082903 1 T1 43 T2 15 T3 46735

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%