Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
594568 |
768503 |
0 |
0 |
T2 |
283240 |
109099 |
0 |
0 |
T3 |
958370 |
402550 |
0 |
0 |
T4 |
56374 |
1602 |
0 |
0 |
T5 |
508892 |
694211 |
0 |
0 |
T6 |
983620 |
526375 |
0 |
0 |
T7 |
319882 |
245817 |
0 |
0 |
T8 |
1355344 |
774886 |
0 |
0 |
T9 |
833728 |
285312 |
0 |
0 |
T10 |
225118 |
13949 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
594568 |
594532 |
0 |
0 |
T2 |
283240 |
283044 |
0 |
0 |
T3 |
958370 |
958340 |
0 |
0 |
T4 |
56374 |
56176 |
0 |
0 |
T5 |
508892 |
508878 |
0 |
0 |
T6 |
983620 |
983602 |
0 |
0 |
T7 |
319882 |
319870 |
0 |
0 |
T8 |
1355344 |
1355164 |
0 |
0 |
T9 |
833728 |
833696 |
0 |
0 |
T10 |
225118 |
224968 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
594568 |
594532 |
0 |
0 |
T2 |
283240 |
283044 |
0 |
0 |
T3 |
958370 |
958340 |
0 |
0 |
T4 |
56374 |
56176 |
0 |
0 |
T5 |
508892 |
508878 |
0 |
0 |
T6 |
983620 |
983602 |
0 |
0 |
T7 |
319882 |
319870 |
0 |
0 |
T8 |
1355344 |
1355164 |
0 |
0 |
T9 |
833728 |
833696 |
0 |
0 |
T10 |
225118 |
224968 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
594568 |
594532 |
0 |
0 |
T2 |
283240 |
283044 |
0 |
0 |
T3 |
958370 |
958340 |
0 |
0 |
T4 |
56374 |
56176 |
0 |
0 |
T5 |
508892 |
508878 |
0 |
0 |
T6 |
983620 |
983602 |
0 |
0 |
T7 |
319882 |
319870 |
0 |
0 |
T8 |
1355344 |
1355164 |
0 |
0 |
T9 |
833728 |
833696 |
0 |
0 |
T10 |
225118 |
224968 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
594568 |
768503 |
0 |
0 |
T2 |
283240 |
109099 |
0 |
0 |
T3 |
958370 |
402550 |
0 |
0 |
T4 |
56374 |
1602 |
0 |
0 |
T5 |
508892 |
694211 |
0 |
0 |
T6 |
983620 |
526375 |
0 |
0 |
T7 |
319882 |
245817 |
0 |
0 |
T8 |
1355344 |
774886 |
0 |
0 |
T9 |
833728 |
285312 |
0 |
0 |
T10 |
225118 |
13949 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1776651578 |
0 |
0 |
T1 |
297284 |
650194 |
0 |
0 |
T2 |
141620 |
0 |
0 |
0 |
T3 |
479185 |
221212 |
0 |
0 |
T4 |
28187 |
10 |
0 |
0 |
T5 |
254446 |
493295 |
0 |
0 |
T6 |
491810 |
378478 |
0 |
0 |
T7 |
159941 |
140562 |
0 |
0 |
T8 |
677672 |
495748 |
0 |
0 |
T9 |
416864 |
161175 |
0 |
0 |
T10 |
112559 |
13152 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
297284 |
297266 |
0 |
0 |
T2 |
141620 |
141522 |
0 |
0 |
T3 |
479185 |
479170 |
0 |
0 |
T4 |
28187 |
28088 |
0 |
0 |
T5 |
254446 |
254439 |
0 |
0 |
T6 |
491810 |
491801 |
0 |
0 |
T7 |
159941 |
159935 |
0 |
0 |
T8 |
677672 |
677582 |
0 |
0 |
T9 |
416864 |
416848 |
0 |
0 |
T10 |
112559 |
112484 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
297284 |
297266 |
0 |
0 |
T2 |
141620 |
141522 |
0 |
0 |
T3 |
479185 |
479170 |
0 |
0 |
T4 |
28187 |
28088 |
0 |
0 |
T5 |
254446 |
254439 |
0 |
0 |
T6 |
491810 |
491801 |
0 |
0 |
T7 |
159941 |
159935 |
0 |
0 |
T8 |
677672 |
677582 |
0 |
0 |
T9 |
416864 |
416848 |
0 |
0 |
T10 |
112559 |
112484 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
297284 |
297266 |
0 |
0 |
T2 |
141620 |
141522 |
0 |
0 |
T3 |
479185 |
479170 |
0 |
0 |
T4 |
28187 |
28088 |
0 |
0 |
T5 |
254446 |
254439 |
0 |
0 |
T6 |
491810 |
491801 |
0 |
0 |
T7 |
159941 |
159935 |
0 |
0 |
T8 |
677672 |
677582 |
0 |
0 |
T9 |
416864 |
416848 |
0 |
0 |
T10 |
112559 |
112484 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1776651578 |
0 |
0 |
T1 |
297284 |
650194 |
0 |
0 |
T2 |
141620 |
0 |
0 |
0 |
T3 |
479185 |
221212 |
0 |
0 |
T4 |
28187 |
10 |
0 |
0 |
T5 |
254446 |
493295 |
0 |
0 |
T6 |
491810 |
378478 |
0 |
0 |
T7 |
159941 |
140562 |
0 |
0 |
T8 |
677672 |
495748 |
0 |
0 |
T9 |
416864 |
161175 |
0 |
0 |
T10 |
112559 |
13152 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9,T12,T13 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T9,T12,T13 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
669486226 |
0 |
0 |
T1 |
297284 |
118309 |
0 |
0 |
T2 |
141620 |
109099 |
0 |
0 |
T3 |
479185 |
181338 |
0 |
0 |
T4 |
28187 |
1592 |
0 |
0 |
T5 |
254446 |
200916 |
0 |
0 |
T6 |
491810 |
147897 |
0 |
0 |
T7 |
159941 |
105255 |
0 |
0 |
T8 |
677672 |
279138 |
0 |
0 |
T9 |
416864 |
124137 |
0 |
0 |
T10 |
112559 |
797 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
297284 |
297266 |
0 |
0 |
T2 |
141620 |
141522 |
0 |
0 |
T3 |
479185 |
479170 |
0 |
0 |
T4 |
28187 |
28088 |
0 |
0 |
T5 |
254446 |
254439 |
0 |
0 |
T6 |
491810 |
491801 |
0 |
0 |
T7 |
159941 |
159935 |
0 |
0 |
T8 |
677672 |
677582 |
0 |
0 |
T9 |
416864 |
416848 |
0 |
0 |
T10 |
112559 |
112484 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
297284 |
297266 |
0 |
0 |
T2 |
141620 |
141522 |
0 |
0 |
T3 |
479185 |
479170 |
0 |
0 |
T4 |
28187 |
28088 |
0 |
0 |
T5 |
254446 |
254439 |
0 |
0 |
T6 |
491810 |
491801 |
0 |
0 |
T7 |
159941 |
159935 |
0 |
0 |
T8 |
677672 |
677582 |
0 |
0 |
T9 |
416864 |
416848 |
0 |
0 |
T10 |
112559 |
112484 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
297284 |
297266 |
0 |
0 |
T2 |
141620 |
141522 |
0 |
0 |
T3 |
479185 |
479170 |
0 |
0 |
T4 |
28187 |
28088 |
0 |
0 |
T5 |
254446 |
254439 |
0 |
0 |
T6 |
491810 |
491801 |
0 |
0 |
T7 |
159941 |
159935 |
0 |
0 |
T8 |
677672 |
677582 |
0 |
0 |
T9 |
416864 |
416848 |
0 |
0 |
T10 |
112559 |
112484 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
669486226 |
0 |
0 |
T1 |
297284 |
118309 |
0 |
0 |
T2 |
141620 |
109099 |
0 |
0 |
T3 |
479185 |
181338 |
0 |
0 |
T4 |
28187 |
1592 |
0 |
0 |
T5 |
254446 |
200916 |
0 |
0 |
T6 |
491810 |
147897 |
0 |
0 |
T7 |
159941 |
105255 |
0 |
0 |
T8 |
677672 |
279138 |
0 |
0 |
T9 |
416864 |
124137 |
0 |
0 |
T10 |
112559 |
797 |
0 |
0 |