Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	10200951	0	0
ctrl_rd_A	2147483647	198401	0	0
intr_enable_rd_A	2147483647	175741	0	0
ovrd_rd_A	2147483647	196509	0	0
timeout_ctrl_rd_A	2147483647	197907	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10200951	0	0
T3	479185	156706	0	0
T4	28187	0	0	0
T5	254446	0	0	0
T6	491810	0	0	0
T7	159941	0	0	0
T8	677672	0	0	0
T9	416864	160834	0	0
T10	112559	0	0	0
T11	44199	0	0	0
T14	0	81174	0	0
T15	0	66034	0	0
T16	0	247541	0	0
T17	0	93983	0	0
T18	0	41334	0	0
T19	0	209613	0	0
T20	0	112087	0	0
T29	0	71369	0	0
T30	276123	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	198401	0	0
T16	0	27338	0	0
T20	466372	12520	0	0
T24	2964	0	0	0
T33	177730	0	0	0
T34	290819	0	0	0
T35	218912	0	0	0
T100	203187	0	0	0
T109	0	1697	0	0
T110	0	9671	0	0
T111	0	5688	0	0
T112	0	9592	0	0
T113	0	5954	0	0
T114	0	5489	0	0
T115	0	18120	0	0
T116	0	5546	0	0
T117	131110	0	0	0
T118	837638	0	0	0
T119	103886	0	0	0
T120	901518	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	175741	0	0
T16	0	24378	0	0
T20	466372	10421	0	0
T24	2964	0	0	0
T33	177730	0	0	0
T34	290819	0	0	0
T35	218912	0	0	0
T100	203187	0	0	0
T109	0	1679	0	0
T110	0	9176	0	0
T111	0	4944	0	0
T112	0	8513	0	0
T113	0	5396	0	0
T114	0	4761	0	0
T115	0	16280	0	0
T117	131110	0	0	0
T118	837638	0	0	0
T119	103886	0	0	0
T120	901518	0	0	0
T121	0	12	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196509	0	0
T16	0	27849	0	0
T20	466372	11718	0	0
T24	2964	0	0	0
T33	177730	0	0	0
T34	290819	0	0	0
T35	218912	0	0	0
T100	203187	0	0	0
T109	0	1853	0	0
T110	0	9440	0	0
T111	0	5824	0	0
T112	0	10154	0	0
T113	0	5813	0	0
T114	0	5405	0	0
T115	0	18257	0	0
T116	0	5051	0	0
T117	131110	0	0	0
T118	837638	0	0	0
T119	103886	0	0	0
T120	901518	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	197907	0	0
T16	0	27471	0	0
T20	466372	12237	0	0
T24	2964	0	0	0
T33	177730	0	0	0
T34	290819	0	0	0
T35	218912	0	0	0
T100	203187	0	0	0
T109	0	1752	0	0
T110	0	9742	0	0
T111	0	5705	0	0
T112	0	10068	0	0
T113	0	6408	0	0
T114	0	5519	0	0
T115	0	18244	0	0
T116	0	5346	0	0
T117	131110	0	0	0
T118	837638	0	0	0
T119	103886	0	0	0
T120	901518	0	0	0