Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	9519308	0	0
ctrl_rd_A	2147483647	169526	0	0
intr_enable_rd_A	2147483647	150792	0	0
ovrd_rd_A	2147483647	169698	0	0
timeout_ctrl_rd_A	2147483647	168979	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9519308	0	0
T12	114708	0	0	0
T15	0	146142	0	0
T16	656130	271214	0	0
T17	0	70611	0	0
T20	0	156580	0	0
T21	461895	0	0	0
T29	108229	40323	0	0
T31	1041	0	0	0
T36	323610	0	0	0
T37	0	193916	0	0
T38	0	194156	0	0
T39	0	157750	0	0
T40	0	220085	0	0
T41	0	224248	0	0
T42	458945	0	0	0
T43	192459	0	0	0
T44	78381	0	0	0
T45	640089	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	169526	0	0
T41	876951	25656	0	0
T99	0	10637	0	0
T100	0	5298	0	0
T101	0	5720	0	0
T102	0	2975	0	0
T103	0	4078	0	0
T104	0	13091	0	0
T105	0	4243	0	0
T106	0	3653	0	0
T107	0	6291	0	0
T108	108817	0	0	0
T109	199755	0	0	0
T110	108572	0	0	0
T111	192560	0	0	0
T112	178036	0	0	0
T113	273899	0	0	0
T114	501328	0	0	0
T115	48881	0	0	0
T116	443920	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	150792	0	0
T41	876951	22492	0	0
T99	0	9502	0	0
T100	0	4843	0	0
T101	0	4907	0	0
T102	0	2959	0	0
T103	0	3368	0	0
T104	0	11812	0	0
T105	0	3652	0	0
T108	108817	0	0	0
T109	199755	0	0	0
T110	108572	0	0	0
T111	192560	0	0	0
T112	178036	0	0	0
T113	273899	0	0	0
T114	501328	0	0	0
T115	48881	0	0	0
T116	443920	0	0	0
T117	0	44	0	0
T118	0	22	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	169698	0	0
T41	876951	25612	0	0
T99	0	10607	0	0
T100	0	5425	0	0
T101	0	6017	0	0
T102	0	3361	0	0
T103	0	4062	0	0
T104	0	12268	0	0
T105	0	3948	0	0
T106	0	3807	0	0
T107	0	6516	0	0
T108	108817	0	0	0
T109	199755	0	0	0
T110	108572	0	0	0
T111	192560	0	0	0
T112	178036	0	0	0
T113	273899	0	0	0
T114	501328	0	0	0
T115	48881	0	0	0
T116	443920	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	168979	0	0
T41	876951	25421	0	0
T99	0	10480	0	0
T100	0	5529	0	0
T101	0	5710	0	0
T102	0	3260	0	0
T103	0	3957	0	0
T104	0	12548	0	0
T105	0	3989	0	0
T106	0	3383	0	0
T107	0	6439	0	0
T108	108817	0	0	0
T109	199755	0	0	0
T110	108572	0	0	0
T111	192560	0	0	0
T112	178036	0	0	0
T113	273899	0	0	0
T114	501328	0	0	0
T115	48881	0	0	0
T116	443920	0	0	0