Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64819198	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24143194

1

T1

17

T2

39

T3

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82986834	1			T1	1712		T2	27		T3	39789
values[0x0]	2831842	1			T1	12		T2	32		T3	18
values[0x1]	3143716	1			T1	10		T2	32		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45246861	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

43715531

1

T1

868

T2

45

T3

19924

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	388254	1			T2	3		T4	5		T6	46
valid_sources[0x01]	353712	1			T3	5243		T4	7		T6	41
valid_sources[0x02]	351471	1			T4	11		T6	54		T8	443
valid_sources[0x03]	346202	1			T1	24		T4	5		T6	53
valid_sources[0x04]	366564	1			T1	8		T4	7		T6	55
valid_sources[0x05]	342715	1			T1	10		T4	10		T6	37
valid_sources[0x06]	325203	1			T4	5		T6	39		T7	1
valid_sources[0x07]	346438	1			T3	320		T4	10		T6	37
valid_sources[0x08]	322728	1			T4	7		T5	36		T6	35
valid_sources[0x09]	317048	1			T1	20		T4	8		T6	51
valid_sources[0x0a]	328997	1			T4	4		T6	36		T8	489
valid_sources[0x0b]	347213	1			T2	5		T4	6		T6	40
valid_sources[0x0c]	321072	1			T1	5		T4	5		T6	40
valid_sources[0x0d]	340885	1			T1	24		T2	1		T4	10
valid_sources[0x0e]	374865	1			T1	15		T3	10212		T4	8
valid_sources[0x0f]	358208	1			T1	34		T2	2		T4	9
valid_sources[0x10]	347191	1			T1	33		T3	1		T4	5
valid_sources[0x11]	323686	1			T4	8		T6	46		T8	445
valid_sources[0x12]	340404	1			T1	30		T4	7		T6	48
valid_sources[0x13]	324952	1			T4	7		T6	49		T8	431
valid_sources[0x14]	326140	1			T1	18		T4	7		T5	85
valid_sources[0x15]	394981	1			T1	28		T4	9		T6	44
valid_sources[0x16]	360633	1			T4	5		T6	36		T8	509
valid_sources[0x17]	407119	1			T4	11		T6	50		T8	484
valid_sources[0x18]	327709	1			T1	16		T4	7		T6	53
valid_sources[0x19]	356570	1			T1	44		T4	4		T6	58
valid_sources[0x1a]	324610	1			T2	1		T4	5		T5	7
valid_sources[0x1b]	382600	1			T4	9		T5	6		T6	45
valid_sources[0x1c]	337146	1			T1	8		T4	5		T6	47
valid_sources[0x1d]	323261	1			T1	7		T4	6		T6	49
valid_sources[0x1e]	333860	1			T4	6		T5	12		T6	46
valid_sources[0x1f]	364378	1			T1	9		T4	5		T6	44
valid_sources[0x20]	397267	1			T1	14		T4	5		T6	40
valid_sources[0x21]	346839	1			T1	5		T2	3		T4	9
valid_sources[0x22]	308694	1			T1	19		T4	5		T6	39
valid_sources[0x23]	333422	1			T1	3		T3	1		T4	5
valid_sources[0x24]	335853	1			T1	17		T4	1		T6	46
valid_sources[0x25]	391410	1			T4	3		T5	6		T6	45
valid_sources[0x26]	339029	1			T1	24		T4	6		T6	49
valid_sources[0x27]	371346	1			T4	13		T5	2		T6	39
valid_sources[0x28]	330758	1			T1	6		T2	7		T4	6
valid_sources[0x29]	349517	1			T1	11		T4	5		T5	25
valid_sources[0x2a]	343494	1			T4	5		T6	49		T8	520
valid_sources[0x2b]	345551	1			T1	3		T4	5		T6	54
valid_sources[0x2c]	386597	1			T1	1		T4	5		T6	49
valid_sources[0x2d]	364777	1			T2	1		T4	5		T6	53
valid_sources[0x2e]	349243	1			T4	4		T6	45		T8	499
valid_sources[0x2f]	524283	1			T4	6		T6	38		T8	431
valid_sources[0x30]	328121	1			T1	8		T4	5		T5	4
valid_sources[0x31]	334278	1			T4	7		T6	56		T8	488
valid_sources[0x32]	633209	1			T2	1		T4	3		T6	54
valid_sources[0x33]	358431	1			T1	15		T4	2		T5	19
valid_sources[0x34]	332425	1			T2	2		T4	3		T5	16
valid_sources[0x35]	376254	1			T4	7		T6	53		T8	500
valid_sources[0x36]	347959	1			T4	7		T5	3		T6	44
valid_sources[0x37]	339495	1			T4	6		T6	42		T8	480
valid_sources[0x38]	331201	1			T1	2		T4	8		T6	31
valid_sources[0x39]	316371	1			T1	23		T4	6		T6	40
valid_sources[0x3a]	356999	1			T4	8		T5	25		T6	45
valid_sources[0x3b]	426046	1			T4	5		T5	16		T6	45
valid_sources[0x3c]	339901	1			T1	13		T4	4		T5	7
valid_sources[0x3d]	380860	1			T1	9		T4	4		T6	59
valid_sources[0x3e]	321764	1			T4	6		T6	53		T8	519
valid_sources[0x3f]	329050	1			T4	3		T6	44		T7	2448
valid_sources[0x40]	337091	1			T4	10		T6	57		T8	444
valid_sources[0x41]	341558	1			T4	4		T6	45		T8	539
valid_sources[0x42]	358671	1			T1	2		T4	7		T5	18
valid_sources[0x43]	335363	1			T1	32		T4	10		T6	43
valid_sources[0x44]	319156	1			T4	11		T5	15		T6	48
valid_sources[0x45]	355645	1			T4	3		T6	52		T8	513
valid_sources[0x46]	325895	1			T4	8		T6	55		T8	473
valid_sources[0x47]	390863	1			T1	5		T4	8		T5	1
valid_sources[0x48]	338393	1			T1	14		T4	4		T6	50
valid_sources[0x49]	359721	1			T1	2		T4	7		T6	45
valid_sources[0x4a]	327783	1			T1	1		T4	6		T6	40
valid_sources[0x4b]	381226	1			T4	6		T6	45		T7	2597
valid_sources[0x4c]	325535	1			T1	9		T2	2		T4	4
valid_sources[0x4d]	325971	1			T1	15		T4	3		T6	56
valid_sources[0x4e]	389251	1			T1	7		T4	12		T6	42
valid_sources[0x4f]	375703	1			T4	4		T5	4		T6	52
valid_sources[0x50]	323063	1			T1	27		T4	3		T6	53
valid_sources[0x51]	333537	1			T4	6		T6	52		T8	525
valid_sources[0x52]	332836	1			T1	23		T2	1		T4	7
valid_sources[0x53]	323134	1			T1	34		T4	6		T6	49
valid_sources[0x54]	355134	1			T4	7		T6	43		T8	485
valid_sources[0x55]	358348	1			T3	4297		T4	6		T5	4
valid_sources[0x56]	328897	1			T1	6		T4	3		T5	24
valid_sources[0x57]	345522	1			T1	4		T4	5		T6	34
valid_sources[0x58]	346136	1			T4	8		T5	3		T6	49
valid_sources[0x59]	357389	1			T1	1		T2	2		T5	5
valid_sources[0x5a]	327527	1			T1	3		T4	4		T6	48
valid_sources[0x5b]	355461	1			T2	1		T4	7		T6	49
valid_sources[0x5c]	359246	1			T1	5		T4	5		T6	50
valid_sources[0x5d]	345603	1			T2	1		T4	5		T6	51
valid_sources[0x5e]	341112	1			T4	7		T6	39		T8	468
valid_sources[0x5f]	339330	1			T1	9		T4	6		T6	54
valid_sources[0x60]	309648	1			T1	1		T4	3		T6	47
valid_sources[0x61]	331789	1			T2	2		T6	35		T8	527
valid_sources[0x62]	339657	1			T1	14		T2	2		T4	1
valid_sources[0x63]	316660	1			T1	1		T4	4		T6	37
valid_sources[0x64]	334504	1			T4	4		T5	25		T6	50
valid_sources[0x65]	339966	1			T1	5		T2	1		T4	6
valid_sources[0x66]	337545	1			T1	20		T4	5		T6	46
valid_sources[0x67]	331275	1			T1	17		T6	36		T8	504
valid_sources[0x68]	353421	1			T2	4		T4	5		T6	37
valid_sources[0x69]	343220	1			T4	3		T6	47		T8	485
valid_sources[0x6a]	342100	1			T4	3		T6	57		T8	483
valid_sources[0x6b]	350657	1			T1	4		T2	1		T4	5
valid_sources[0x6c]	370257	1			T1	2		T4	7		T5	9
valid_sources[0x6d]	355958	1			T4	4		T6	41		T7	2599
valid_sources[0x6e]	335344	1			T1	8		T4	9		T5	35
valid_sources[0x6f]	340190	1			T4	3		T6	26		T8	479
valid_sources[0x70]	350567	1			T1	15		T2	4		T4	6
valid_sources[0x71]	311766	1			T4	8		T6	36		T8	476
valid_sources[0x72]	312873	1			T1	54		T4	8		T6	52
valid_sources[0x73]	329438	1			T4	8		T6	46		T8	480
valid_sources[0x74]	338660	1			T1	6		T4	8		T6	45
valid_sources[0x75]	336230	1			T1	15		T2	1		T4	8
valid_sources[0x76]	368589	1			T1	16		T3	9900		T4	7
valid_sources[0x77]	335097	1			T4	7		T5	1		T6	36
valid_sources[0x78]	325110	1			T4	3		T6	36		T8	487
valid_sources[0x79]	358254	1			T1	18		T4	5		T5	1
valid_sources[0x7a]	321657	1			T1	5		T4	7		T5	1
valid_sources[0x7b]	336885	1			T4	8		T6	53		T8	468
valid_sources[0x7c]	338124	1			T4	1		T6	42		T7	2450
valid_sources[0x7d]	344325	1			T1	12		T4	10		T6	57
valid_sources[0x7e]	342229	1			T1	19		T4	5		T6	55
valid_sources[0x7f]	341311	1			T2	2		T4	5		T6	30
valid_sources[0x80]	314204	1			T1	15		T4	5		T5	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18958642

1

T2

12

T4

31

T5

86

values[0x0]

all_enables

biggest_size

2618189

1

T1

11

T2

16

T3

10

values[0x1]

all_enables

biggest_size

2566363

1

T1

6

T2

11

T3

17