Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	8358112	0	0
ctrl_rd_A	2147483647	248240	0	0
intr_enable_rd_A	2147483647	220965	0	0
ovrd_rd_A	2147483647	247044	0	0
timeout_ctrl_rd_A	2147483647	246543	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8358112	0	0
T8	846328	34878	0	0
T9	85615	0	0	0
T10	545910	133815	0	0
T11	299317	0	0	0
T12	921341	0	0	0
T13	62722	0	0	0
T14	371847	149762	0	0
T25	0	235842	0	0
T26	0	174294	0	0
T27	0	89776	0	0
T28	0	75038	0	0
T29	0	154491	0	0
T30	0	176597	0	0
T31	0	78026	0	0
T32	852984	0	0	0
T33	668937	0	0	0
T34	937021	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	248240	0	0
T10	545910	14164	0	0
T11	299317	0	0	0
T12	921341	0	0	0
T13	62722	0	0	0
T14	371847	0	0	0
T15	525884	0	0	0
T25	780041	0	0	0
T26	0	19207	0	0
T27	0	8094	0	0
T29	0	17429	0	0
T32	852984	0	0	0
T33	668937	0	0	0
T34	937021	0	0	0
T52	0	16023	0	0
T53	0	8284	0	0
T120	0	4291	0	0
T121	0	798	0	0
T122	0	5860	0	0
T123	0	11790	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	220965	0	0
T10	545910	12305	0	0
T11	299317	0	0	0
T12	921341	0	0	0
T13	62722	0	0	0
T14	371847	0	0	0
T15	525884	0	0	0
T25	780041	0	0	0
T26	0	17030	0	0
T27	0	7589	0	0
T29	0	16265	0	0
T32	852984	0	0	0
T33	668937	0	0	0
T34	937021	0	0	0
T46	0	1	0	0
T52	0	13796	0	0
T53	0	7230	0	0
T120	0	3756	0	0
T121	0	572	0	0
T124	0	31	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	247044	0	0
T10	545910	14235	0	0
T11	299317	0	0	0
T12	921341	0	0	0
T13	62722	0	0	0
T14	371847	0	0	0
T15	525884	0	0	0
T25	780041	0	0	0
T26	0	19402	0	0
T27	0	8450	0	0
T29	0	17368	0	0
T32	852984	0	0	0
T33	668937	0	0	0
T34	937021	0	0	0
T52	0	15800	0	0
T53	0	8688	0	0
T120	0	4490	0	0
T121	0	659	0	0
T122	0	6206	0	0
T123	0	11747	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	246543	0	0
T10	545910	14309	0	0
T11	299317	0	0	0
T12	921341	0	0	0
T13	62722	0	0	0
T14	371847	0	0	0
T15	525884	0	0	0
T25	780041	0	0	0
T26	0	19079	0	0
T27	0	8649	0	0
T29	0	18067	0	0
T32	852984	0	0	0
T33	668937	0	0	0
T34	937021	0	0	0
T52	0	15668	0	0
T53	0	8403	0	0
T120	0	4027	0	0
T121	0	819	0	0
T122	0	6027	0	0
T123	0	11209	0	0