Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59516393	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

18510013

1

T1

30

T2

131

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	72230250	1			T1	229		T2	4603		T3	2719
values[0x0]	2744968	1			T1	17		T2	181		T3	3
values[0x1]	3051188	1			T1	21		T2	169		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41005432	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37020974

1

T1

120

T2

1644

T3

1331

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	294503	1			T2	29		T3	2		T5	22
valid_sources[0x01]	265112	1			T2	20		T5	17		T6	497
valid_sources[0x02]	309414	1			T1	2		T2	25		T3	45
valid_sources[0x03]	333716	1			T2	14		T5	15		T6	1249
valid_sources[0x04]	302344	1			T2	7		T5	14		T6	2229
valid_sources[0x05]	261859	1			T2	4		T3	52		T5	15
valid_sources[0x06]	343263	1			T1	1		T2	4		T3	45
valid_sources[0x07]	285012	1			T1	1		T2	27		T5	16
valid_sources[0x08]	282799	1			T1	2		T2	19		T3	21
valid_sources[0x09]	300537	1			T1	1		T2	9		T5	31
valid_sources[0x0a]	266265	1			T1	2		T2	21		T3	18
valid_sources[0x0b]	300471	1			T1	2		T2	16		T3	91
valid_sources[0x0c]	263025	1			T2	16		T3	5		T5	12
valid_sources[0x0d]	281836	1			T2	14		T3	13		T5	21
valid_sources[0x0e]	333883	1			T1	3		T2	23		T5	18
valid_sources[0x0f]	279992	1			T2	24		T3	12		T5	20
valid_sources[0x10]	262843	1			T2	16		T3	23		T5	32
valid_sources[0x11]	293646	1			T1	1		T2	12		T5	22
valid_sources[0x12]	289483	1			T2	34		T5	19		T6	490
valid_sources[0x13]	273943	1			T1	1		T2	28		T3	28
valid_sources[0x14]	315423	1			T1	5		T2	19		T5	18
valid_sources[0x15]	273258	1			T1	2		T2	14		T5	21
valid_sources[0x16]	332527	1			T2	36		T5	13		T6	898
valid_sources[0x17]	280794	1			T2	1		T3	4		T5	25
valid_sources[0x18]	289260	1			T2	31		T5	23		T6	751
valid_sources[0x19]	290190	1			T1	3		T2	7		T3	34
valid_sources[0x1a]	276641	1			T2	6		T5	19		T6	278
valid_sources[0x1b]	262057	1			T1	2		T2	6		T3	8
valid_sources[0x1c]	285674	1			T1	1		T2	15		T5	13
valid_sources[0x1d]	290414	1			T1	4		T2	31		T3	5
valid_sources[0x1e]	302819	1			T1	1		T2	11		T5	17
valid_sources[0x1f]	312625	1			T1	2		T2	3		T3	9
valid_sources[0x20]	359425	1			T1	1		T2	8		T3	17
valid_sources[0x21]	290754	1			T1	1		T2	25		T3	13
valid_sources[0x22]	261767	1			T1	1		T2	21		T3	31
valid_sources[0x23]	280177	1			T2	24		T3	5		T5	27
valid_sources[0x24]	290727	1			T1	1		T2	27		T3	5
valid_sources[0x25]	306228	1			T1	1		T2	7		T3	16
valid_sources[0x26]	279783	1			T2	9		T5	12		T6	1666
valid_sources[0x27]	288918	1			T2	27		T5	21		T6	1433
valid_sources[0x28]	310893	1			T1	3		T2	23		T5	14
valid_sources[0x29]	259601	1			T1	1		T2	2		T3	8
valid_sources[0x2a]	291083	1			T2	7		T3	9		T5	20
valid_sources[0x2b]	343980	1			T2	31		T5	13		T6	688
valid_sources[0x2c]	287959	1			T1	1		T2	6		T5	10
valid_sources[0x2d]	323346	1			T1	1		T2	13		T5	13
valid_sources[0x2e]	287584	1			T1	2		T2	27		T5	25
valid_sources[0x2f]	292186	1			T1	1		T2	7		T5	23
valid_sources[0x30]	324213	1			T1	1		T2	9		T3	9
valid_sources[0x31]	272137	1			T1	2		T2	13		T3	7
valid_sources[0x32]	293497	1			T1	1		T2	23		T3	13
valid_sources[0x33]	299596	1			T1	1		T2	21		T3	2
valid_sources[0x34]	261829	1			T1	1		T2	51		T3	16
valid_sources[0x35]	265891	1			T1	2		T2	35		T5	23
valid_sources[0x36]	293560	1			T2	57		T3	62		T5	27
valid_sources[0x37]	296009	1			T1	1		T2	13		T3	6
valid_sources[0x38]	273434	1			T1	1		T2	23		T3	44
valid_sources[0x39]	276705	1			T1	1		T2	36		T5	23
valid_sources[0x3a]	351977	1			T1	1		T2	11		T3	5
valid_sources[0x3b]	262001	1			T2	22		T5	23		T6	5061
valid_sources[0x3c]	289284	1			T1	3		T2	8		T3	14
valid_sources[0x3d]	264008	1			T1	1		T2	32		T5	22
valid_sources[0x3e]	286517	1			T1	3		T2	28		T5	20
valid_sources[0x3f]	322262	1			T1	2		T2	24		T5	18
valid_sources[0x40]	263302	1			T1	1		T2	30		T5	22
valid_sources[0x41]	283083	1			T1	2		T2	14		T5	18
valid_sources[0x42]	309481	1			T1	1		T2	14		T5	23
valid_sources[0x43]	285763	1			T1	1		T2	1		T3	8
valid_sources[0x44]	267532	1			T1	2		T2	3		T5	13
valid_sources[0x45]	329160	1			T2	5		T5	21		T6	4032
valid_sources[0x46]	265540	1			T5	26		T6	723		T7	291
valid_sources[0x47]	307569	1			T1	1		T2	21		T5	23
valid_sources[0x48]	290762	1			T2	8		T3	12		T5	27
valid_sources[0x49]	288154	1			T1	1		T2	14		T3	49
valid_sources[0x4a]	273322	1			T1	1		T2	4		T3	10
valid_sources[0x4b]	317249	1			T2	27		T5	13		T6	797
valid_sources[0x4c]	305380	1			T1	1		T2	24		T3	9
valid_sources[0x4d]	276816	1			T1	1		T2	21		T3	5
valid_sources[0x4e]	299671	1			T1	1		T2	14		T5	20
valid_sources[0x4f]	281998	1			T2	70		T3	13		T5	16
valid_sources[0x50]	282343	1			T2	22		T3	3		T5	15
valid_sources[0x51]	313368	1			T2	11		T5	20		T6	675
valid_sources[0x52]	277031	1			T1	3		T2	21		T5	24
valid_sources[0x53]	257803	1			T1	1		T2	36		T3	13
valid_sources[0x54]	281445	1			T1	1		T2	43		T3	5
valid_sources[0x55]	266669	1			T2	12		T3	15		T5	18
valid_sources[0x56]	367340	1			T2	3		T5	22		T6	1391
valid_sources[0x57]	273772	1			T2	17		T3	5		T5	24
valid_sources[0x58]	355077	1			T1	4		T2	28		T3	1
valid_sources[0x59]	281757	1			T1	1		T2	25		T3	14
valid_sources[0x5a]	283840	1			T1	1		T2	20		T3	71
valid_sources[0x5b]	303563	1			T1	1		T2	13		T3	23
valid_sources[0x5c]	314816	1			T1	1		T2	29		T5	19
valid_sources[0x5d]	318746	1			T1	4		T2	23		T5	22
valid_sources[0x5e]	289892	1			T1	1		T2	30		T3	54
valid_sources[0x5f]	266899	1			T1	1		T2	5		T3	8
valid_sources[0x60]	264718	1			T1	4		T2	44		T5	11
valid_sources[0x61]	274240	1			T1	1		T2	27		T5	24
valid_sources[0x62]	287174	1			T2	3		T5	18		T6	363
valid_sources[0x63]	308095	1			T2	14		T5	18		T6	1145
valid_sources[0x64]	281379	1			T2	11		T3	8		T5	15
valid_sources[0x65]	290096	1			T2	15		T3	3		T5	25
valid_sources[0x66]	280155	1			T1	1		T2	31		T3	6
valid_sources[0x67]	450533	1			T1	1		T2	17		T3	9
valid_sources[0x68]	273939	1			T2	26		T3	25		T5	19
valid_sources[0x69]	276587	1			T1	3		T2	49		T5	16
valid_sources[0x6a]	292378	1			T1	4		T2	30		T4	4385
valid_sources[0x6b]	302104	1			T1	1		T2	59		T5	34
valid_sources[0x6c]	280201	1			T1	4		T2	34		T5	29
valid_sources[0x6d]	319168	1			T2	26		T3	19		T5	22
valid_sources[0x6e]	280233	1			T1	4		T2	24		T3	41
valid_sources[0x6f]	311822	1			T1	2		T2	6		T5	17
valid_sources[0x70]	286023	1			T1	1		T2	3		T3	5
valid_sources[0x71]	420309	1			T2	16		T3	42		T5	17
valid_sources[0x72]	335559	1			T2	37		T3	69		T5	16
valid_sources[0x73]	285303	1			T1	1		T2	31		T3	23
valid_sources[0x74]	271861	1			T1	1		T2	30		T5	33
valid_sources[0x75]	291723	1			T1	1		T2	7		T3	37
valid_sources[0x76]	312244	1			T2	21		T3	7		T5	22
valid_sources[0x77]	277408	1			T2	29		T3	45		T5	16
valid_sources[0x78]	257622	1			T2	24		T5	20		T6	516
valid_sources[0x79]	275645	1			T1	3		T2	20		T3	4
valid_sources[0x7a]	270224	1			T1	3		T2	9		T3	2
valid_sources[0x7b]	319863	1			T1	1		T2	16		T5	18
valid_sources[0x7c]	336702	1			T2	5		T3	10		T5	15
valid_sources[0x7d]	294652	1			T2	15		T5	20		T6	1343
valid_sources[0x7e]	510517	1			T1	2		T2	8		T5	25
valid_sources[0x7f]	309185	1			T1	1		T2	22		T5	21
valid_sources[0x80]	309569	1			T1	2		T2	12		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13482207

1

T1

3

T2

31

T3

1

values[0x0]

all_enables

biggest_size

2538443

1

T1

13

T2

65

T3

2

values[0x1]

all_enables

biggest_size

2489363

1

T1

14

T2

35

T3

2