Unified Coverage Report :: Module :: prim_fifo_sync_cnt

Module : prim_fifo_sync_cnt

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_core.u_uart_txfifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00
tb.dut.uart_core.u_uart_rxfifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.uart_core.u_uart_txfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.75	100.00	75.00			100.00	100.00	u_uart_txfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.uart_core.u_uart_rxfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.75	100.00	75.00			100.00	100.00	u_uart_rxfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=32,Secure=0,PtrW=5,DepthW=6,WrapPtrW=6 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.uart_core.u_uart_txfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		27	27	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
ALWAYS	113	8	8	100.00
ALWAYS	125	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	1	1
42	1	1
46	1	1
47	1	1
51	1	1
52	1	1
55	1	1
56	1	1
59	1	1
61	1	1
68	1	1
113	1	1
114	1	1
115	1	1
116	1	1
117	1	1
118	1	1
119	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=64,Secure=0,PtrW=6,DepthW=7,WrapPtrW=7 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.uart_core.u_uart_rxfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		27	27	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
ALWAYS	113	8	8	100.00
ALWAYS	125	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	1	1
42	1	1
46	1	1
47	1	1
51	1	1
52	1	1
55	1	1
56	1	1
59	1	1
61	1	1
68	1	1
113	1	1
114	1	1
115	1	1
116	1	1
117	1	1
118	1	1
119	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=32,Secure=0,PtrW=5,DepthW=6,WrapPtrW=6 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.uart_core.u_uart_txfifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	20	20	100.00
Logical	20	20	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 5'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T6,T8

 LINE       51
 SUB-EXPRESSION (wptr_o == 5'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T8

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 5'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T6,T8

 LINE       52
 SUB-EXPRESSION (rptr_o == 5'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T8

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T8

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T8

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T6,T8
1	Covered	T1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T6,T8
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=64,Secure=0,PtrW=6,DepthW=7,WrapPtrW=7 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.uart_core.u_uart_rxfifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	20	20	100.00
Logical	20	20	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T11
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T10,T11

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T10,T11

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T11,T12

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T11,T12

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T14,T15

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (7'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((7'(wptr_o) - 7'(rptr_o))) : (((7'(Depth) - 7'(rptr_o)) + 7'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T14,T15

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((7'(wptr_o) - 7'(rptr_o))) : (((7'(Depth) - 7'(rptr_o)) + 7'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T6,T10,T11
1	Covered	T1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T6,T10,T11
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync_cnt

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	68	3	3	100.00
IF	113	5	5	100.00
IF	125	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T6,T8
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T6,T8

	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T2,T6,T8
0	0	0	1	Covered	T1,T2,T4
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T2,T6,T8
0	0	0	1	Covered	T1,T2,T4
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.uart_core.u_uart_txfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		27	27	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
ALWAYS	113	8	8	100.00
ALWAYS	125	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	1	1
42	1	1
46	1	1
47	1	1
51	1	1
52	1	1
55	1	1
56	1	1
59	1	1
61	1	1
68	1	1
113	1	1
114	1	1
115	1	1
116	1	1
117	1	1
118	1	1
119	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.uart_core.u_uart_txfifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	20	20	100.00
Logical	20	20	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 5'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T6,T8

 LINE       51
 SUB-EXPRESSION (wptr_o == 5'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T8

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 5'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T6,T8

 LINE       52
 SUB-EXPRESSION (rptr_o == 5'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T8

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T8

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (6'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T8

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((6'(wptr_o) - 6'(rptr_o))) : (((6'(Depth) - 6'(rptr_o)) + 6'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T6,T8
1	Covered	T1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T6,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.uart_core.u_uart_txfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	68	3	3	100.00
IF	113	5	5	100.00
IF	125	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T6,T8
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T6,T8

	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T5,T6
0	0	1	-	Covered	T2,T6,T8
0	0	0	1	Covered	T1,T2,T4
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T5,T6
0	0	1	-	Covered	T2,T6,T8
0	0	0	1	Covered	T1,T2,T4
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		27	27	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
ALWAYS	113	8	8	100.00
ALWAYS	125	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	1	1
42	1	1
46	1	1
47	1	1
51	1	1
52	1	1
55	1	1
56	1	1
59	1	1
61	1	1
68	1	1
113	1	1
114	1	1
115	1	1
116	1	1
117	1	1
118	1	1
119	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	20	20	100.00
Logical	20	20	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T11
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T10,T11

 LINE       51
 SUB-EXPRESSION (wptr_o == 6'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T10,T11

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 6'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T11,T12

 LINE       52
 SUB-EXPRESSION (rptr_o == 6'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T11,T12

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T14,T15

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (7'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((7'(wptr_o) - 7'(rptr_o))) : (((7'(Depth) - 7'(rptr_o)) + 7'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T14,T15

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((7'(wptr_o) - 7'(rptr_o))) : (((7'(Depth) - 7'(rptr_o)) + 7'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T6,T10,T11
1	Covered	T1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T6,T10,T11
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	68	3	3	100.00
IF	113	5	5	100.00
IF	125	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T10,T14,T15
0	1	Covered	T1,T2,T3
0	0	Covered	T6,T10,T11

	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T6,T10,T11
0	0	0	1	Covered	T1,T2,T4
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T6,T11,T12
0	0	0	1	Covered	T1,T2,T4
0	0	0	0	Covered	T1,T2,T3