Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	8149814	0	0
ctrl_rd_A	2147483647	181132	0	0
intr_enable_rd_A	2147483647	161170	0	0
ovrd_rd_A	2147483647	181737	0	0
timeout_ctrl_rd_A	2147483647	180771	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8149814	0	0
T6	205788	82419	0	0
T7	596434	0	0	0
T8	762342	0	0	0
T9	26066	0	0	0
T10	157925	0	0	0
T11	718569	0	0	0
T12	531915	0	0	0
T13	460697	0	0	0
T16	0	81306	0	0
T19	0	129268	0	0
T22	0	131351	0	0
T29	0	232620	0	0
T30	0	27591	0	0
T31	0	138897	0	0
T32	0	55403	0	0
T33	0	327539	0	0
T34	0	32974	0	0
T35	816580	0	0	0
T36	409375	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	181132	0	0
T22	553309	5923	0	0
T24	1137	0	0	0
T26	5134	0	0	0
T30	0	3294	0	0
T39	213831	0	0	0
T97	100144	0	0	0
T98	888771	0	0	0
T99	135485	0	0	0
T100	112594	0	0	0
T101	104593	0	0	0
T102	387832	0	0	0
T104	0	7889	0	0
T105	0	16647	0	0
T106	0	1649	0	0
T107	0	4995	0	0
T108	0	5504	0	0
T109	0	15025	0	0
T110	0	12229	0	0
T111	0	6947	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	161170	0	0
T22	553309	5480	0	0
T24	1137	0	0	0
T26	5134	0	0	0
T30	0	2956	0	0
T39	213831	0	0	0
T97	100144	0	0	0
T98	888771	0	0	0
T99	135485	0	0	0
T100	112594	0	0	0
T101	104593	0	0	0
T102	387832	0	0	0
T104	0	7116	0	0
T105	0	14090	0	0
T106	0	1685	0	0
T107	0	4595	0	0
T108	0	4820	0	0
T112	0	19	0	0
T113	0	17	0	0
T114	0	4	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	181737	0	0
T22	553309	5957	0	0
T24	1137	0	0	0
T26	5134	0	0	0
T30	0	3366	0	0
T39	213831	0	0	0
T97	100144	0	0	0
T98	888771	0	0	0
T99	135485	0	0	0
T100	112594	0	0	0
T101	104593	0	0	0
T102	387832	0	0	0
T104	0	7786	0	0
T105	0	16612	0	0
T106	0	1770	0	0
T107	0	5064	0	0
T108	0	5314	0	0
T109	0	15393	0	0
T110	0	12598	0	0
T111	0	6971	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	180771	0	0
T22	553309	5738	0	0
T24	1137	0	0	0
T26	5134	0	0	0
T30	0	3282	0	0
T39	213831	0	0	0
T97	100144	0	0	0
T98	888771	0	0	0
T99	135485	0	0	0
T100	112594	0	0	0
T101	104593	0	0	0
T102	387832	0	0	0
T104	0	8005	0	0
T105	0	16858	0	0
T106	0	1936	0	0
T107	0	5025	0	0
T108	0	5220	0	0
T109	0	15415	0	0
T110	0	11901	0	0
T111	0	6976	0	0