Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	69270366	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

21876426

1

T1

28

T2

122

T4

302

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	85312009	1			T1	292		T2	2880		T3	1
values[0x0]	2766013	1			T1	11		T2	132		T4	144
values[0x1]	3068770	1			T1	19		T2	141		T4	151

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47956914	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

43189878

1

T1

143

T2

1060

T4

2313

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	346184	1			T2	26		T4	40		T6	120
valid_sources[0x01]	355224	1			T2	5		T4	18		T6	75
valid_sources[0x02]	475078	1			T1	2		T2	5		T4	16
valid_sources[0x03]	336928	1			T2	1		T4	32		T6	83
valid_sources[0x04]	338657	1			T2	28		T4	26		T6	86
valid_sources[0x05]	440034	1			T1	1		T2	7		T4	24
valid_sources[0x06]	340721	1			T4	26		T6	89		T8	1474
valid_sources[0x07]	366600	1			T1	3		T2	2		T4	34
valid_sources[0x08]	333492	1			T2	37		T4	17		T6	86
valid_sources[0x09]	358879	1			T2	10		T4	24		T6	72
valid_sources[0x0a]	342512	1			T2	14		T4	20		T6	80
valid_sources[0x0b]	468279	1			T1	2		T2	27		T4	38
valid_sources[0x0c]	416384	1			T2	4		T4	15		T6	117
valid_sources[0x0d]	337209	1			T1	2		T2	14		T4	31
valid_sources[0x0e]	353162	1			T1	1		T2	15		T4	27
valid_sources[0x0f]	349149	1			T1	3		T2	5		T4	27
valid_sources[0x10]	361297	1			T1	3		T4	20		T6	60
valid_sources[0x11]	338369	1			T1	4		T4	18		T6	96
valid_sources[0x12]	403697	1			T4	19		T6	75		T8	1295
valid_sources[0x13]	334157	1			T2	6		T4	37		T6	106
valid_sources[0x14]	350981	1			T2	13		T4	28		T6	83
valid_sources[0x15]	380888	1			T1	1		T2	18		T4	10
valid_sources[0x16]	380124	1			T1	1		T2	30		T4	26
valid_sources[0x17]	334123	1			T4	36		T6	61		T8	1502
valid_sources[0x18]	343496	1			T2	56		T4	16		T6	105
valid_sources[0x19]	350975	1			T2	6		T4	16		T6	97
valid_sources[0x1a]	331991	1			T2	40		T4	13		T6	113
valid_sources[0x1b]	375437	1			T1	2		T2	15		T4	35
valid_sources[0x1c]	331805	1			T1	8		T2	5		T4	25
valid_sources[0x1d]	336282	1			T1	1		T2	13		T4	21
valid_sources[0x1e]	329787	1			T1	2		T2	21		T4	31
valid_sources[0x1f]	339371	1			T2	2		T4	25		T6	70
valid_sources[0x20]	371592	1			T1	1		T2	2		T4	19
valid_sources[0x21]	544560	1			T1	1		T2	24		T4	28
valid_sources[0x22]	342825	1			T2	18		T4	23		T6	132
valid_sources[0x23]	343423	1			T1	7		T2	7		T4	19
valid_sources[0x24]	346091	1			T2	11		T4	29		T6	77
valid_sources[0x25]	333273	1			T2	3		T4	23		T6	98
valid_sources[0x26]	344300	1			T2	11		T4	26		T6	95
valid_sources[0x27]	335553	1			T1	2		T2	11		T4	18
valid_sources[0x28]	401267	1			T4	33		T6	105		T8	1458
valid_sources[0x29]	388404	1			T2	3		T4	27		T6	112
valid_sources[0x2a]	421828	1			T2	6		T4	15		T6	133
valid_sources[0x2b]	382674	1			T2	23		T4	13		T6	89
valid_sources[0x2c]	367227	1			T2	27		T3	1		T4	26
valid_sources[0x2d]	337957	1			T2	4		T4	28		T6	85
valid_sources[0x2e]	372395	1			T1	1		T2	8		T4	25
valid_sources[0x2f]	362181	1			T1	1		T2	22		T4	29
valid_sources[0x30]	363560	1			T1	1		T2	16		T4	18
valid_sources[0x31]	388007	1			T1	1		T2	11		T4	22
valid_sources[0x32]	447837	1			T1	1		T2	3		T4	27
valid_sources[0x33]	346240	1			T2	7		T4	25		T6	74
valid_sources[0x34]	338030	1			T2	3		T4	24		T6	133
valid_sources[0x35]	358838	1			T1	2		T2	2		T4	30
valid_sources[0x36]	348212	1			T1	5		T2	11		T4	22
valid_sources[0x37]	370754	1			T1	1		T2	10		T4	31
valid_sources[0x38]	415624	1			T2	2		T4	24		T6	76
valid_sources[0x39]	374464	1			T1	6		T2	6		T4	24
valid_sources[0x3a]	347877	1			T1	1		T2	14		T4	27
valid_sources[0x3b]	332930	1			T1	4		T2	6		T4	16
valid_sources[0x3c]	330944	1			T1	3		T2	24		T4	34
valid_sources[0x3d]	326746	1			T1	2		T2	18		T4	34
valid_sources[0x3e]	346711	1			T2	8		T4	18		T6	87
valid_sources[0x3f]	339608	1			T2	37		T4	28		T6	101
valid_sources[0x40]	340908	1			T1	1		T2	3		T4	31
valid_sources[0x41]	409584	1			T1	1		T2	4		T4	30
valid_sources[0x42]	352872	1			T2	12		T4	20		T6	96
valid_sources[0x43]	342907	1			T1	1		T2	18		T4	23
valid_sources[0x44]	363944	1			T1	2		T2	33		T4	27
valid_sources[0x45]	356967	1			T1	1		T2	40		T4	26
valid_sources[0x46]	391421	1			T4	27		T6	92		T8	1509
valid_sources[0x47]	345634	1			T1	1		T4	23		T6	101
valid_sources[0x48]	434509	1			T2	2		T4	27		T6	84
valid_sources[0x49]	375455	1			T1	3		T4	20		T6	83
valid_sources[0x4a]	366904	1			T2	5		T4	29		T6	101
valid_sources[0x4b]	347313	1			T2	10		T4	26		T6	95
valid_sources[0x4c]	384840	1			T1	4		T4	21		T6	60
valid_sources[0x4d]	377771	1			T1	2		T2	33		T4	34
valid_sources[0x4e]	350216	1			T2	3		T4	20		T6	95
valid_sources[0x4f]	366871	1			T2	11		T4	24		T6	87
valid_sources[0x50]	354154	1			T1	3		T4	22		T6	86
valid_sources[0x51]	333286	1			T1	7		T2	8		T4	26
valid_sources[0x52]	334514	1			T2	8		T4	29		T6	111
valid_sources[0x53]	387632	1			T1	2		T2	14		T4	35
valid_sources[0x54]	350359	1			T1	1		T2	10		T4	17
valid_sources[0x55]	337467	1			T2	9		T4	21		T6	109
valid_sources[0x56]	345811	1			T2	14		T4	35		T6	76
valid_sources[0x57]	333046	1			T2	18		T4	23		T6	97
valid_sources[0x58]	346907	1			T2	12		T4	18		T6	85
valid_sources[0x59]	346527	1			T1	1		T2	9		T4	15
valid_sources[0x5a]	324202	1			T2	18		T4	15		T6	74
valid_sources[0x5b]	342698	1			T2	1		T4	18		T6	85
valid_sources[0x5c]	347487	1			T2	3		T4	19		T6	110
valid_sources[0x5d]	349868	1			T1	4		T2	9		T4	21
valid_sources[0x5e]	347367	1			T1	4		T2	40		T4	27
valid_sources[0x5f]	340468	1			T2	3		T4	43		T6	70
valid_sources[0x60]	343717	1			T2	1		T4	29		T6	94
valid_sources[0x61]	334714	1			T2	8		T4	29		T6	64
valid_sources[0x62]	454962	1			T1	3		T2	30		T4	37
valid_sources[0x63]	338051	1			T1	1		T2	2		T4	22
valid_sources[0x64]	336753	1			T2	35		T4	32		T6	67
valid_sources[0x65]	328821	1			T1	2		T2	11		T4	17
valid_sources[0x66]	374248	1			T1	1		T4	23		T6	62
valid_sources[0x67]	346379	1			T2	25		T4	26		T6	84
valid_sources[0x68]	335991	1			T2	8		T4	40		T6	106
valid_sources[0x69]	352432	1			T2	27		T4	34		T6	93
valid_sources[0x6a]	386903	1			T1	2		T2	27		T4	17
valid_sources[0x6b]	344176	1			T1	11		T2	6		T4	14
valid_sources[0x6c]	406182	1			T1	3		T2	11		T4	36
valid_sources[0x6d]	476631	1			T2	18		T4	21		T6	75
valid_sources[0x6e]	358989	1			T2	2		T4	20		T6	77
valid_sources[0x6f]	329913	1			T2	15		T4	26		T6	85
valid_sources[0x70]	337987	1			T4	22		T6	81		T8	1512
valid_sources[0x71]	346104	1			T2	9		T4	29		T6	53
valid_sources[0x72]	371636	1			T1	1		T2	13		T4	13
valid_sources[0x73]	326052	1			T1	1		T2	5		T4	12
valid_sources[0x74]	380946	1			T2	3		T4	31		T6	84
valid_sources[0x75]	330848	1			T1	1		T2	3		T4	20
valid_sources[0x76]	351799	1			T2	7		T4	41		T6	99
valid_sources[0x77]	346725	1			T4	22		T6	96		T8	1469
valid_sources[0x78]	429647	1			T1	2		T2	12		T4	21
valid_sources[0x79]	331949	1			T1	2		T4	28		T6	79
valid_sources[0x7a]	337904	1			T1	1		T2	5		T4	40
valid_sources[0x7b]	360923	1			T1	1		T2	13		T4	26
valid_sources[0x7c]	343267	1			T1	4		T2	30		T4	10
valid_sources[0x7d]	352951	1			T1	2		T2	29		T4	12
valid_sources[0x7e]	327540	1			T2	3		T4	20		T6	103
valid_sources[0x7f]	358110	1			T2	23		T4	27		T6	93
valid_sources[0x80]	337077	1			T4	26		T6	55		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16852168

1

T1

3

T2

48

T4

196

values[0x0]

all_enables

biggest_size

2539160

1

T1

10

T2

45

T4

69

values[0x1]

all_enables

biggest_size

2485098

1

T1

15

T2

29

T4

37