Module Definition
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Module : uart_rx
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_rx.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.uart_core.uart_rx 100.00 100.00 100.00 100.00



Module Instance : tb.dut.uart_core.uart_rx

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.98 98.94 99.04 97.96 100.00 uart_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : uart_rx
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
ALWAYS381111100.00
ALWAYS542626100.00
ALWAYS9333100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_rx.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_rx.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
MISSING_ELSE
70 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
77 1 1
78 1 1
81 1 1
82 1 1
84 1 1
85 1 1
86 1 1
MISSING_ELSE
93 2 2
94 1 1
98 1 1
99 1 1
101 1 1
102 1 1


Cond Coverage for Module : uart_rx
TotalCoveredPercent
Conditions2929100.00
Logical2929100.00
Non-Logical00
Event00

 LINE       70
 EXPRESSION (idle_q && ((!rx)))
             ---1--    ---2---
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       74
 EXPRESSION (parity_enable ? 4'd11 : 4'd10)
             ------1------
-1-StatusTests
0CoveredT2,T4,T6
1CoveredT1,T2,T5

 LINE       77
 EXPRESSION (((!idle_q)) && tick_baud_q)
             -----1-----    -----2-----
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       78
 EXPRESSION ((bit_cnt_q == (parity_enable ? 4'd11 : 4'd10)) && rx)
             -----------------------1----------------------    -2
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT7,T8,T9

 LINE       78
 SUB-EXPRESSION (bit_cnt_q == (parity_enable ? 4'd11 : 4'd10))
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       86
 EXPRESSION (bit_cnt_q == 4'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       94
 EXPRESSION (tick_baud_q & (bit_cnt_q == 4'b1))
             -----1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       94
 SUB-EXPRESSION (bit_cnt_q == 4'b1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       99
 EXPRESSION (parity_enable ? sreg_q[8:1] : sreg_q[9:2])
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       101
 EXPRESSION (rx_valid_q & ((~sreg_q[10])))
             -----1----   -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT8,T9,T17

 LINE       102
 EXPRESSION (parity_enable & rx_valid_q & ((^{sreg_q[9:1], parity_odd})))
             ------1------   -----2----   ---------------3--------------
-1--2--3-StatusTests
011CoveredT2,T4,T6
101CoveredT1,T2,T5
110CoveredT1,T2,T5
111CoveredT8,T9,T16

Branch Coverage for Module : uart_rx
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 99 2 2 100.00
IF 38 2 2 100.00
IF 54 8 8 100.00
IF 93 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_rx.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_rx.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 99 (parity_enable) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 38 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 54 if ((!rx_enable)) -2-: 66 if (tick_baud_x16) -3-: 70 if ((idle_q && (!rx))) -4-: 74 (parity_enable) ? -5-: 77 if (((!idle_q) && tick_baud_q)) -6-: 78 if (((bit_cnt_q == (parity_enable ? 4'd11 : 4'd10)) && rx))

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 - - - - Covered T1,T2,T4
0 0 - - - - Covered T1,T2,T4
0 - 1 1 - - Covered T1,T2,T5
0 - 1 0 - - Covered T2,T4,T6
0 - 0 - 1 1 Covered T7,T8,T9
0 - 0 - 1 0 Covered T1,T2,T4
0 - 0 - 0 - Covered T1,T2,T4


LineNo. Expression -1-: 93 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%