Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	8099936	0	0
ctrl_rd_A	2147483647	186665	0	0
intr_enable_rd_A	2147483647	166146	0	0
ovrd_rd_A	2147483647	186201	0	0
timeout_ctrl_rd_A	2147483647	184814	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8099936	0	0
T8	157548	322558	0	0
T9	133052	0	0	0
T10	154423	0	0	0
T11	244771	0	0	0
T12	293528	0	0	0
T13	151669	0	0	0
T14	357234	0	0	0
T15	0	55542	0	0
T16	923444	244118	0	0
T21	0	204163	0	0
T27	0	89862	0	0
T28	0	137828	0	0
T29	0	118924	0	0
T30	0	116188	0	0
T31	0	178095	0	0
T32	0	61233	0	0
T33	109734	0	0	0
T34	411900	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	186665	0	0
T8	157548	34764	0	0
T9	133052	0	0	0
T10	154423	0	0	0
T11	244771	0	0	0
T12	293528	0	0	0
T13	151669	0	0	0
T14	357234	0	0	0
T16	923444	13125	0	0
T29	0	14020	0	0
T33	109734	0	0	0
T34	411900	0	0	0
T43	0	5052	0	0
T44	0	6532	0	0
T83	0	997	0	0
T84	0	3927	0	0
T85	0	11115	0	0
T86	0	889	0	0
T87	0	19818	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	166146	0	0
T8	157548	30624	0	0
T9	133052	0	0	0
T10	154423	0	0	0
T11	244771	0	0	0
T12	293528	0	0	0
T13	151669	0	0	0
T14	357234	0	0	0
T16	923444	11763	0	0
T29	0	12238	0	0
T33	109734	0	0	0
T34	411900	0	0	0
T43	0	4398	0	0
T44	0	5624	0	0
T71	0	35	0	0
T83	0	856	0	0
T84	0	3448	0	0
T85	0	10162	0	0
T88	0	41	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	186201	0	0
T8	157548	35510	0	0
T9	133052	0	0	0
T10	154423	0	0	0
T11	244771	0	0	0
T12	293528	0	0	0
T13	151669	0	0	0
T14	357234	0	0	0
T16	923444	12594	0	0
T29	0	13655	0	0
T33	109734	0	0	0
T34	411900	0	0	0
T43	0	4786	0	0
T44	0	6155	0	0
T83	0	1091	0	0
T84	0	3859	0	0
T85	0	11623	0	0
T86	0	993	0	0
T87	0	19970	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	184814	0	0
T8	157548	34520	0	0
T9	133052	0	0	0
T10	154423	0	0	0
T11	244771	0	0	0
T12	293528	0	0	0
T13	151669	0	0	0
T14	357234	0	0	0
T16	923444	13156	0	0
T29	0	13678	0	0
T33	109734	0	0	0
T34	411900	0	0	0
T43	0	5000	0	0
T44	0	6204	0	0
T83	0	971	0	0
T84	0	3633	0	0
T85	0	11490	0	0
T86	0	888	0	0
T87	0	19816	0	0