Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14322671	0	0
ctrl_rd_A	2147483647	305398	0	0
intr_enable_rd_A	2147483647	270892	0	0
ovrd_rd_A	2147483647	302990	0	0
timeout_ctrl_rd_A	2147483647	303670	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14322671	0	0
T8	106940	183891	0	0
T9	703930	0	0	0
T10	659266	0	0	0
T11	167495	0	0	0
T12	197690	80896	0	0
T15	616603	152090	0	0
T16	0	124302	0	0
T19	0	233625	0	0
T20	0	115162	0	0
T22	0	80883	0	0
T28	0	52039	0	0
T29	0	97804	0	0
T30	0	145235	0	0
T31	268908	0	0	0
T32	227003	0	0	0
T33	24047	0	0	0
T34	159357	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	305398	0	0
T8	106940	20222	0	0
T9	703930	0	0	0
T10	659266	0	0	0
T11	167495	0	0	0
T12	197690	0	0	0
T15	616603	0	0	0
T28	0	2670	0	0
T29	0	4743	0	0
T31	268908	0	0	0
T32	227003	0	0	0
T33	24047	0	0	0
T34	159357	0	0	0
T39	0	4388	0	0
T40	0	3245	0	0
T41	0	13678	0	0
T87	0	10784	0	0
T88	0	19148	0	0
T89	0	5164	0	0
T90	0	10764	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	270892	0	0
T8	106940	17749	0	0
T9	703930	0	0	0
T10	659266	0	0	0
T11	167495	0	0	0
T12	197690	0	0	0
T15	616603	0	0	0
T28	0	2421	0	0
T29	0	4511	0	0
T31	268908	0	0	0
T32	227003	0	0	0
T33	24047	0	0	0
T34	159357	0	0	0
T39	0	3568	0	0
T40	0	3051	0	0
T41	0	11860	0	0
T87	0	9376	0	0
T88	0	17304	0	0
T89	0	4595	0	0
T90	0	9228	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	302990	0	0
T8	106940	20508	0	0
T9	703930	0	0	0
T10	659266	0	0	0
T11	167495	0	0	0
T12	197690	0	0	0
T15	616603	0	0	0
T28	0	2664	0	0
T29	0	5033	0	0
T31	268908	0	0	0
T32	227003	0	0	0
T33	24047	0	0	0
T34	159357	0	0	0
T39	0	4023	0	0
T40	0	2977	0	0
T41	0	13033	0	0
T87	0	10755	0	0
T88	0	19915	0	0
T89	0	4935	0	0
T90	0	10485	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	303670	0	0
T8	106940	20864	0	0
T9	703930	0	0	0
T10	659266	0	0	0
T11	167495	0	0	0
T12	197690	0	0	0
T15	616603	0	0	0
T28	0	2802	0	0
T29	0	5124	0	0
T31	268908	0	0	0
T32	227003	0	0	0
T33	24047	0	0	0
T34	159357	0	0	0
T39	0	4231	0	0
T40	0	2861	0	0
T41	0	13263	0	0
T87	0	10203	0	0
T88	0	19561	0	0
T89	0	5344	0	0
T90	0	10592	0	0