Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	70048564	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28093829

1

T1

10

T2

121401

T3

160

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	87980651	1			T1	32		T2	39409		T3	2526
values[0x0]	4808527	1			T1	7		T2	46064		T3	129
values[0x1]	5353215	1			T1	6		T2	51924		T3	138

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48445348	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

49697045

1

T1

23

T2

128676

T3

997

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	372191	1			T2	455		T3	28		T4	16
valid_sources[0x01]	377433	1			T2	684		T3	12		T4	13
valid_sources[0x02]	377195	1			T2	822		T3	3		T4	10
valid_sources[0x03]	364124	1			T2	423		T3	9		T4	5
valid_sources[0x04]	375498	1			T2	535		T3	10		T4	6
valid_sources[0x05]	377499	1			T2	403		T4	8		T6	1
valid_sources[0x06]	383229	1			T1	9		T2	121		T4	4
valid_sources[0x07]	409151	1			T2	578		T3	2		T4	4
valid_sources[0x08]	519010	1			T2	501		T3	9		T4	8
valid_sources[0x09]	416159	1			T2	275		T3	23		T4	9
valid_sources[0x0a]	367961	1			T2	283		T3	3		T4	10
valid_sources[0x0b]	354351	1			T2	275		T4	7		T7	8
valid_sources[0x0c]	398923	1			T2	861		T4	9		T7	4
valid_sources[0x0d]	392595	1			T2	702		T3	11		T4	10
valid_sources[0x0e]	365150	1			T2	657		T3	18		T4	6
valid_sources[0x0f]	353931	1			T2	242		T3	23		T4	12
valid_sources[0x10]	398894	1			T2	598		T3	1		T4	8
valid_sources[0x11]	365159	1			T2	745		T4	11		T7	5
valid_sources[0x12]	378356	1			T2	629		T3	14		T4	4
valid_sources[0x13]	375095	1			T2	92		T3	3		T4	3
valid_sources[0x14]	346945	1			T2	731		T3	2		T4	13
valid_sources[0x15]	365812	1			T2	878		T3	4		T4	15
valid_sources[0x16]	361812	1			T2	746		T3	12		T4	20
valid_sources[0x17]	375152	1			T1	4		T2	1151		T3	15
valid_sources[0x18]	372225	1			T2	462		T3	3		T4	7
valid_sources[0x19]	387728	1			T2	687		T3	12		T4	4
valid_sources[0x1a]	392613	1			T2	595		T3	3		T4	6
valid_sources[0x1b]	358375	1			T2	593		T4	12		T7	4
valid_sources[0x1c]	371322	1			T1	2		T2	173		T3	11
valid_sources[0x1d]	390039	1			T2	813		T3	3		T4	16
valid_sources[0x1e]	391651	1			T2	149		T3	6		T4	4
valid_sources[0x1f]	371974	1			T2	791		T3	2		T4	11
valid_sources[0x20]	374330	1			T2	709		T3	24		T4	8
valid_sources[0x21]	366407	1			T2	535		T3	12		T4	7
valid_sources[0x22]	387748	1			T2	396		T3	23		T4	12
valid_sources[0x23]	369628	1			T2	809		T4	7		T7	2
valid_sources[0x24]	383875	1			T2	272		T3	13		T4	7
valid_sources[0x25]	388332	1			T2	481		T3	6		T4	7
valid_sources[0x26]	378631	1			T2	702		T3	50		T4	14
valid_sources[0x27]	398504	1			T2	380		T3	3		T4	10
valid_sources[0x28]	359136	1			T2	354		T3	51		T4	7
valid_sources[0x29]	376299	1			T2	541		T4	14		T6	1
valid_sources[0x2a]	377145	1			T2	316		T3	12		T4	5
valid_sources[0x2b]	389236	1			T2	428		T3	2		T4	8
valid_sources[0x2c]	371527	1			T2	153		T4	10		T7	4
valid_sources[0x2d]	378014	1			T2	58		T3	16		T4	7
valid_sources[0x2e]	387499	1			T2	127		T3	9		T4	11
valid_sources[0x2f]	403089	1			T2	244		T3	3		T4	15
valid_sources[0x30]	354489	1			T2	270		T4	9		T7	2
valid_sources[0x31]	383878	1			T2	504		T3	27		T4	8
valid_sources[0x32]	365659	1			T2	538		T4	13		T7	7
valid_sources[0x33]	384297	1			T2	692		T3	2		T4	11
valid_sources[0x34]	397957	1			T2	214		T3	38		T4	10
valid_sources[0x35]	366485	1			T1	4		T2	1029		T3	21
valid_sources[0x36]	365632	1			T2	224		T3	16		T4	15
valid_sources[0x37]	412564	1			T2	885		T3	6		T4	7
valid_sources[0x38]	386225	1			T2	586		T4	10		T7	3
valid_sources[0x39]	358693	1			T2	266		T4	7		T7	7
valid_sources[0x3a]	377559	1			T2	745		T3	8		T4	10
valid_sources[0x3b]	362345	1			T2	388		T3	1		T4	7
valid_sources[0x3c]	433177	1			T2	311		T3	14		T4	12
valid_sources[0x3d]	395625	1			T2	195		T3	13		T4	12
valid_sources[0x3e]	361610	1			T2	269		T3	5		T4	12
valid_sources[0x3f]	381465	1			T2	879		T3	9		T4	4
valid_sources[0x40]	410492	1			T1	2		T2	450		T3	2
valid_sources[0x41]	349752	1			T2	566		T3	1		T4	12
valid_sources[0x42]	524440	1			T2	802		T3	12		T4	6
valid_sources[0x43]	381823	1			T2	774		T3	5		T4	19
valid_sources[0x44]	447628	1			T2	178		T3	26		T4	4
valid_sources[0x45]	512465	1			T2	537		T3	20		T4	7
valid_sources[0x46]	360112	1			T2	244		T4	9		T7	9
valid_sources[0x47]	436815	1			T2	981		T3	2		T4	6
valid_sources[0x48]	377415	1			T1	1		T2	1003		T3	9
valid_sources[0x49]	422325	1			T1	1		T2	317		T3	17
valid_sources[0x4a]	367405	1			T2	563		T3	9		T4	5
valid_sources[0x4b]	370067	1			T2	848		T3	16		T4	3
valid_sources[0x4c]	371945	1			T2	1274		T3	12		T4	5
valid_sources[0x4d]	416368	1			T2	304		T3	5		T4	7
valid_sources[0x4e]	388075	1			T1	1		T2	219		T3	13
valid_sources[0x4f]	380020	1			T2	422		T3	11		T4	4
valid_sources[0x50]	375444	1			T2	607		T3	4		T4	14
valid_sources[0x51]	368776	1			T2	599		T4	7		T7	4
valid_sources[0x52]	399293	1			T2	395		T3	56		T4	10
valid_sources[0x53]	364346	1			T2	280		T3	2		T4	10
valid_sources[0x54]	367315	1			T2	478		T4	4		T7	5
valid_sources[0x55]	391034	1			T1	1		T2	424		T3	3
valid_sources[0x56]	356857	1			T2	207		T3	1		T4	7
valid_sources[0x57]	365508	1			T2	832		T3	5		T4	10
valid_sources[0x58]	377191	1			T1	1		T2	547		T3	6
valid_sources[0x59]	361178	1			T2	981		T3	4		T4	14
valid_sources[0x5a]	377070	1			T2	909		T3	11		T4	13
valid_sources[0x5b]	350871	1			T2	1041		T4	7		T7	3
valid_sources[0x5c]	396288	1			T2	321		T3	12		T4	10
valid_sources[0x5d]	438117	1			T1	1		T2	950		T3	6
valid_sources[0x5e]	362063	1			T2	327		T3	12		T4	4
valid_sources[0x5f]	465818	1			T2	720		T3	12		T4	8
valid_sources[0x60]	371969	1			T1	1		T2	42		T3	21
valid_sources[0x61]	409839	1			T2	80		T3	14		T4	10
valid_sources[0x62]	365802	1			T2	774		T3	6		T4	8
valid_sources[0x63]	360332	1			T2	404		T3	14		T4	8
valid_sources[0x64]	397870	1			T2	472		T3	14		T4	5
valid_sources[0x65]	381792	1			T2	124		T3	35		T4	15
valid_sources[0x66]	377372	1			T2	900		T3	3		T4	21
valid_sources[0x67]	402093	1			T2	155		T3	19		T4	14
valid_sources[0x68]	354543	1			T2	103		T3	7		T4	6
valid_sources[0x69]	380923	1			T2	244		T3	14		T4	8
valid_sources[0x6a]	451655	1			T2	224		T3	2		T4	15
valid_sources[0x6b]	357890	1			T2	1280		T4	8		T7	4
valid_sources[0x6c]	369052	1			T2	453		T3	6		T4	16
valid_sources[0x6d]	367633	1			T2	225		T3	10		T4	8
valid_sources[0x6e]	373922	1			T1	1		T2	1138		T3	23
valid_sources[0x6f]	369730	1			T2	852		T3	3		T4	15
valid_sources[0x70]	394129	1			T2	497		T3	4		T4	10
valid_sources[0x71]	380613	1			T2	364		T3	3		T4	7
valid_sources[0x72]	374359	1			T2	507		T3	27		T4	8
valid_sources[0x73]	349946	1			T2	1035		T3	6		T4	9
valid_sources[0x74]	376420	1			T2	694		T3	24		T4	9
valid_sources[0x75]	420971	1			T2	370		T3	2		T4	6
valid_sources[0x76]	363488	1			T2	311		T3	12		T4	7
valid_sources[0x77]	373676	1			T2	553		T3	24		T4	8
valid_sources[0x78]	368530	1			T1	2		T2	169		T3	5
valid_sources[0x79]	398406	1			T2	787		T3	22		T4	7
valid_sources[0x7a]	371606	1			T2	220		T3	1		T4	4
valid_sources[0x7b]	366378	1			T2	312		T3	8		T4	12
valid_sources[0x7c]	364735	1			T2	255		T3	6		T4	17
valid_sources[0x7d]	365493	1			T2	358		T3	6		T4	10
valid_sources[0x7e]	358957	1			T2	351		T3	18		T4	11
valid_sources[0x7f]	466239	1			T2	257		T3	17		T4	4
valid_sources[0x80]	422020	1			T2	199		T3	1		T4	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19084014

1

T1

5

T2

30500

T3

78

values[0x0]

all_enables

biggest_size

4539456

1

T1

3

T2

45438

T3

55

values[0x1]

all_enables

biggest_size

4470359

1

T1

2

T2

45463

T3

27