Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14805561	0	0
ctrl_rd_A	2147483647	280648	0	0
intr_enable_rd_A	2147483647	251602	0	0
ovrd_rd_A	2147483647	278759	0	0
timeout_ctrl_rd_A	2147483647	279593	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14805561	0	0
T2	464692	153849	0	0
T3	207084	0	0	0
T4	33627	0	0	0
T5	111460	0	0	0
T6	364929	0	0	0
T7	190046	0	0	0
T8	918841	0	0	0
T9	637736	0	0	0
T10	798835	0	0	0
T11	136242	0	0	0
T13	0	186070	0	0
T14	0	155275	0	0
T19	0	274371	0	0
T28	0	390873	0	0
T29	0	143251	0	0
T30	0	132878	0	0
T31	0	146870	0	0
T32	0	208053	0	0
T33	0	119399	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	280648	0	0
T29	609518	16059	0	0
T30	312482	0	0	0
T38	0	12633	0	0
T39	0	14061	0	0
T40	0	25276	0	0
T57	288195	0	0	0
T58	117232	0	0	0
T59	860893	0	0	0
T60	1048	0	0	0
T61	8123	0	0	0
T62	46920	0	0	0
T63	18362	0	0	0
T64	17236	0	0	0
T99	0	3817	0	0
T100	0	15687	0	0
T101	0	4022	0	0
T102	0	25026	0	0
T103	0	6444	0	0
T104	0	1675	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	251602	0	0
T29	609518	14486	0	0
T30	312482	0	0	0
T38	0	10972	0	0
T39	0	12567	0	0
T40	0	22664	0	0
T57	288195	0	0	0
T58	117232	0	0	0
T59	860893	0	0	0
T60	1048	0	0	0
T61	8123	0	0	0
T62	46920	0	0	0
T63	18362	0	0	0
T64	17236	0	0	0
T99	0	3684	0	0
T100	0	13926	0	0
T101	0	3840	0	0
T102	0	21658	0	0
T105	0	18	0	0
T106	0	15	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	278759	0	0
T29	609518	16349	0	0
T30	312482	0	0	0
T38	0	12439	0	0
T39	0	13840	0	0
T40	0	25729	0	0
T57	288195	0	0	0
T58	117232	0	0	0
T59	860893	0	0	0
T60	1048	0	0	0
T61	8123	0	0	0
T62	46920	0	0	0
T63	18362	0	0	0
T64	17236	0	0	0
T99	0	4137	0	0
T100	0	15661	0	0
T101	0	4146	0	0
T102	0	24140	0	0
T103	0	6537	0	0
T104	0	1550	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	279593	0	0
T29	609518	16737	0	0
T30	312482	0	0	0
T38	0	12112	0	0
T39	0	13806	0	0
T40	0	25847	0	0
T57	288195	0	0	0
T58	117232	0	0	0
T59	860893	0	0	0
T60	1048	0	0	0
T61	8123	0	0	0
T62	46920	0	0	0
T63	18362	0	0	0
T64	17236	0	0	0
T99	0	3968	0	0
T100	0	15744	0	0
T101	0	4192	0	0
T102	0	24406	0	0
T103	0	6430	0	0
T104	0	1567	0	0