Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 72366341 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 27551463 1 T1 363 T2 170 T3 261



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 90292137 1 T1 80426 T2 3851 T3 122505
values[0x0] 4548435 1 T1 167 T2 170 T3 159
values[0x1] 5077232 1 T1 171 T2 160 T3 127



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 50049757 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 49868047 1 T1 27120 T2 1475 T3 41202



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 361462 1 T1 341 T2 13 T4 70
valid_sources[0x01] 365409 1 T1 352 T2 16 T4 53
valid_sources[0x02] 388507 1 T1 349 T2 17 T4 57
valid_sources[0x03] 366373 1 T1 318 T2 15 T4 73
valid_sources[0x04] 353701 1 T1 338 T2 18 T4 68
valid_sources[0x05] 388258 1 T1 352 T2 26 T4 83
valid_sources[0x06] 361262 1 T1 291 T2 14 T4 55
valid_sources[0x07] 369341 1 T1 348 T2 15 T4 66
valid_sources[0x08] 640347 1 T1 339 T2 22 T4 102
valid_sources[0x09] 368047 1 T1 323 T2 22 T4 67
valid_sources[0x0a] 402036 1 T1 295 T2 24 T4 84
valid_sources[0x0b] 404729 1 T1 325 T2 10 T4 58
valid_sources[0x0c] 426783 1 T1 299 T2 19 T4 89
valid_sources[0x0d] 389644 1 T1 307 T2 13 T4 62
valid_sources[0x0e] 385611 1 T1 326 T2 18 T4 60
valid_sources[0x0f] 400767 1 T1 304 T2 16 T4 65
valid_sources[0x10] 384197 1 T1 351 T2 13 T4 58
valid_sources[0x11] 378828 1 T1 309 T2 21 T4 71
valid_sources[0x12] 384455 1 T1 315 T2 18 T4 72
valid_sources[0x13] 366572 1 T1 302 T2 22 T4 55
valid_sources[0x14] 378316 1 T1 299 T2 18 T4 89
valid_sources[0x15] 367396 1 T1 273 T2 18 T4 81
valid_sources[0x16] 410498 1 T1 301 T2 10 T4 56
valid_sources[0x17] 390691 1 T1 321 T2 15 T3 7597
valid_sources[0x18] 482060 1 T1 353 T2 17 T4 66
valid_sources[0x19] 384689 1 T1 319 T2 13 T4 65
valid_sources[0x1a] 466364 1 T1 311 T2 14 T4 59
valid_sources[0x1b] 368929 1 T1 324 T2 14 T4 54
valid_sources[0x1c] 407872 1 T1 282 T2 21 T4 58
valid_sources[0x1d] 420231 1 T1 353 T2 10 T4 40
valid_sources[0x1e] 372458 1 T1 299 T2 21 T4 43
valid_sources[0x1f] 438638 1 T1 329 T2 9 T3 76092
valid_sources[0x20] 370959 1 T1 309 T2 20 T4 62
valid_sources[0x21] 355824 1 T1 304 T2 22 T4 69
valid_sources[0x22] 374619 1 T1 291 T2 23 T4 65
valid_sources[0x23] 384939 1 T1 292 T2 19 T4 73
valid_sources[0x24] 385680 1 T1 322 T2 17 T4 40
valid_sources[0x25] 375386 1 T1 318 T2 14 T4 87
valid_sources[0x26] 367124 1 T1 307 T2 15 T4 49
valid_sources[0x27] 391792 1 T1 308 T2 13 T4 72
valid_sources[0x28] 382682 1 T1 351 T2 14 T4 50
valid_sources[0x29] 437539 1 T1 302 T2 13 T4 88
valid_sources[0x2a] 427610 1 T1 317 T2 14 T4 83
valid_sources[0x2b] 366295 1 T1 309 T2 14 T4 66
valid_sources[0x2c] 417239 1 T1 313 T2 17 T4 52
valid_sources[0x2d] 372630 1 T1 327 T2 16 T4 92
valid_sources[0x2e] 363297 1 T1 310 T2 20 T4 31
valid_sources[0x2f] 372822 1 T1 296 T2 15 T4 68
valid_sources[0x30] 372688 1 T1 287 T2 19 T4 66
valid_sources[0x31] 382035 1 T1 319 T2 22 T4 61
valid_sources[0x32] 407927 1 T1 296 T2 22 T4 54
valid_sources[0x33] 360506 1 T1 322 T2 17 T4 88
valid_sources[0x34] 343467 1 T1 346 T2 16 T4 57
valid_sources[0x35] 400437 1 T1 315 T2 16 T4 58
valid_sources[0x36] 359251 1 T1 277 T2 18 T4 89
valid_sources[0x37] 369741 1 T1 343 T2 26 T4 89
valid_sources[0x38] 400570 1 T1 329 T2 16 T4 68
valid_sources[0x39] 357224 1 T1 349 T2 14 T4 81
valid_sources[0x3a] 408764 1 T1 312 T2 11 T4 55
valid_sources[0x3b] 369092 1 T1 314 T2 20 T4 79
valid_sources[0x3c] 376587 1 T1 324 T2 15 T4 67
valid_sources[0x3d] 428378 1 T1 287 T2 14 T4 45
valid_sources[0x3e] 446117 1 T1 322 T2 12 T3 18169
valid_sources[0x3f] 383402 1 T1 317 T2 26 T4 52
valid_sources[0x40] 360137 1 T1 286 T2 16 T4 50
valid_sources[0x41] 383541 1 T1 300 T2 18 T4 50
valid_sources[0x42] 355840 1 T1 303 T2 13 T4 75
valid_sources[0x43] 458595 1 T1 306 T2 14 T4 86
valid_sources[0x44] 360029 1 T1 309 T2 11 T4 41
valid_sources[0x45] 646846 1 T1 297 T2 15 T4 63
valid_sources[0x46] 396239 1 T1 306 T2 6 T4 95
valid_sources[0x47] 374575 1 T1 347 T2 20 T4 76
valid_sources[0x48] 424721 1 T1 337 T2 17 T4 44
valid_sources[0x49] 353847 1 T1 297 T2 14 T4 45
valid_sources[0x4a] 365448 1 T1 282 T2 19 T4 68
valid_sources[0x4b] 385314 1 T1 337 T2 15 T4 54
valid_sources[0x4c] 360049 1 T1 289 T2 9 T4 77
valid_sources[0x4d] 347452 1 T1 357 T2 18 T4 75
valid_sources[0x4e] 387895 1 T1 289 T2 8 T4 51
valid_sources[0x4f] 355510 1 T1 314 T2 14 T4 87
valid_sources[0x50] 374362 1 T1 303 T2 17 T4 44
valid_sources[0x51] 391479 1 T1 345 T2 18 T4 68
valid_sources[0x52] 375796 1 T1 336 T2 10 T4 88
valid_sources[0x53] 363284 1 T1 287 T2 15 T4 51
valid_sources[0x54] 398550 1 T1 347 T2 17 T4 42
valid_sources[0x55] 364978 1 T1 333 T2 19 T4 55
valid_sources[0x56] 410543 1 T1 278 T2 15 T4 78
valid_sources[0x57] 391755 1 T1 343 T2 9 T4 82
valid_sources[0x58] 353228 1 T1 314 T2 19 T4 86
valid_sources[0x59] 487312 1 T1 327 T2 18 T4 72
valid_sources[0x5a] 397398 1 T1 325 T2 13 T4 75
valid_sources[0x5b] 358637 1 T1 313 T2 21 T4 71
valid_sources[0x5c] 367357 1 T1 321 T2 13 T4 68
valid_sources[0x5d] 368207 1 T1 347 T2 11 T4 64
valid_sources[0x5e] 412079 1 T1 344 T2 15 T3 5
valid_sources[0x5f] 384282 1 T1 319 T2 7 T4 70
valid_sources[0x60] 395354 1 T1 343 T2 17 T4 77
valid_sources[0x61] 366568 1 T1 345 T2 15 T4 80
valid_sources[0x62] 399142 1 T1 322 T2 13 T4 61
valid_sources[0x63] 376255 1 T1 279 T2 20 T4 74
valid_sources[0x64] 387162 1 T1 280 T2 16 T3 9242
valid_sources[0x65] 359298 1 T1 340 T2 15 T4 78
valid_sources[0x66] 362546 1 T1 376 T2 9 T4 100
valid_sources[0x67] 380037 1 T1 284 T2 19 T4 65
valid_sources[0x68] 428795 1 T1 296 T2 8 T4 51
valid_sources[0x69] 437542 1 T1 331 T2 15 T4 60
valid_sources[0x6a] 455635 1 T1 312 T2 17 T4 41
valid_sources[0x6b] 360687 1 T1 339 T2 16 T4 72
valid_sources[0x6c] 382267 1 T1 326 T2 17 T4 62
valid_sources[0x6d] 443592 1 T1 319 T2 28 T4 104
valid_sources[0x6e] 350231 1 T1 300 T2 23 T4 94
valid_sources[0x6f] 398585 1 T1 311 T2 18 T3 8099
valid_sources[0x70] 356674 1 T1 321 T2 9 T4 71
valid_sources[0x71] 381923 1 T1 286 T2 25 T4 62
valid_sources[0x72] 441681 1 T1 309 T2 19 T4 48
valid_sources[0x73] 370758 1 T1 325 T2 11 T4 53
valid_sources[0x74] 378208 1 T1 328 T2 14 T4 75
valid_sources[0x75] 380140 1 T1 291 T2 24 T4 99
valid_sources[0x76] 382078 1 T1 304 T2 23 T4 56
valid_sources[0x77] 391532 1 T1 299 T2 8 T4 63
valid_sources[0x78] 376601 1 T1 298 T2 13 T4 67
valid_sources[0x79] 398709 1 T1 328 T2 13 T4 70
valid_sources[0x7a] 358064 1 T1 315 T2 9 T4 68
valid_sources[0x7b] 362685 1 T1 339 T2 20 T4 49
valid_sources[0x7c] 373528 1 T1 282 T2 15 T4 63
valid_sources[0x7d] 389197 1 T1 281 T2 15 T4 52
valid_sources[0x7e] 362439 1 T1 360 T2 15 T4 64
valid_sources[0x7f] 460561 1 T1 313 T2 14 T4 71
valid_sources[0x80] 385404 1 T1 322 T2 14 T4 57



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 19051168 1 T1 243 T2 84 T3 164
values[0x0] all_enables biggest_size 4279176 1 T1 63 T2 53 T3 71
values[0x1] all_enables biggest_size 4221119 1 T1 57 T2 33 T3 26

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%