Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
688904 |
378524 |
0 |
0 |
T2 |
833642 |
375605 |
0 |
0 |
T3 |
210274 |
757051 |
0 |
0 |
T4 |
493554 |
284500 |
0 |
0 |
T5 |
396120 |
1229306 |
0 |
0 |
T6 |
896628 |
471323 |
0 |
0 |
T7 |
298258 |
7601 |
0 |
0 |
T8 |
436500 |
280744 |
0 |
0 |
T9 |
1568718 |
1136239 |
0 |
0 |
T10 |
701650 |
999357 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
688904 |
688892 |
0 |
0 |
T2 |
833642 |
833632 |
0 |
0 |
T3 |
210274 |
210272 |
0 |
0 |
T4 |
493554 |
493540 |
0 |
0 |
T5 |
396120 |
396102 |
0 |
0 |
T6 |
896628 |
896610 |
0 |
0 |
T7 |
298258 |
298124 |
0 |
0 |
T8 |
436500 |
436480 |
0 |
0 |
T9 |
1568718 |
1568690 |
0 |
0 |
T10 |
701650 |
701634 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
688904 |
688892 |
0 |
0 |
T2 |
833642 |
833632 |
0 |
0 |
T3 |
210274 |
210272 |
0 |
0 |
T4 |
493554 |
493540 |
0 |
0 |
T5 |
396120 |
396102 |
0 |
0 |
T6 |
896628 |
896610 |
0 |
0 |
T7 |
298258 |
298124 |
0 |
0 |
T8 |
436500 |
436480 |
0 |
0 |
T9 |
1568718 |
1568690 |
0 |
0 |
T10 |
701650 |
701634 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
688904 |
688892 |
0 |
0 |
T2 |
833642 |
833632 |
0 |
0 |
T3 |
210274 |
210272 |
0 |
0 |
T4 |
493554 |
493540 |
0 |
0 |
T5 |
396120 |
396102 |
0 |
0 |
T6 |
896628 |
896610 |
0 |
0 |
T7 |
298258 |
298124 |
0 |
0 |
T8 |
436500 |
436480 |
0 |
0 |
T9 |
1568718 |
1568690 |
0 |
0 |
T10 |
701650 |
701634 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
688904 |
378524 |
0 |
0 |
T2 |
833642 |
375605 |
0 |
0 |
T3 |
210274 |
757051 |
0 |
0 |
T4 |
493554 |
284500 |
0 |
0 |
T5 |
396120 |
1229306 |
0 |
0 |
T6 |
896628 |
471323 |
0 |
0 |
T7 |
298258 |
7601 |
0 |
0 |
T8 |
436500 |
280744 |
0 |
0 |
T9 |
1568718 |
1136239 |
0 |
0 |
T10 |
701650 |
999357 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_txfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1950443098 |
0 |
0 |
T1 |
344452 |
192797 |
0 |
0 |
T2 |
416821 |
121402 |
0 |
0 |
T3 |
105137 |
425430 |
0 |
0 |
T4 |
246777 |
216344 |
0 |
0 |
T5 |
198060 |
919367 |
0 |
0 |
T6 |
448314 |
175051 |
0 |
0 |
T7 |
149129 |
10 |
0 |
0 |
T8 |
218250 |
167823 |
0 |
0 |
T9 |
784359 |
542153 |
0 |
0 |
T10 |
350825 |
300082 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
344452 |
344446 |
0 |
0 |
T2 |
416821 |
416816 |
0 |
0 |
T3 |
105137 |
105136 |
0 |
0 |
T4 |
246777 |
246770 |
0 |
0 |
T5 |
198060 |
198051 |
0 |
0 |
T6 |
448314 |
448305 |
0 |
0 |
T7 |
149129 |
149062 |
0 |
0 |
T8 |
218250 |
218240 |
0 |
0 |
T9 |
784359 |
784345 |
0 |
0 |
T10 |
350825 |
350817 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
344452 |
344446 |
0 |
0 |
T2 |
416821 |
416816 |
0 |
0 |
T3 |
105137 |
105136 |
0 |
0 |
T4 |
246777 |
246770 |
0 |
0 |
T5 |
198060 |
198051 |
0 |
0 |
T6 |
448314 |
448305 |
0 |
0 |
T7 |
149129 |
149062 |
0 |
0 |
T8 |
218250 |
218240 |
0 |
0 |
T9 |
784359 |
784345 |
0 |
0 |
T10 |
350825 |
350817 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
344452 |
344446 |
0 |
0 |
T2 |
416821 |
416816 |
0 |
0 |
T3 |
105137 |
105136 |
0 |
0 |
T4 |
246777 |
246770 |
0 |
0 |
T5 |
198060 |
198051 |
0 |
0 |
T6 |
448314 |
448305 |
0 |
0 |
T7 |
149129 |
149062 |
0 |
0 |
T8 |
218250 |
218240 |
0 |
0 |
T9 |
784359 |
784345 |
0 |
0 |
T10 |
350825 |
350817 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1950443098 |
0 |
0 |
T1 |
344452 |
192797 |
0 |
0 |
T2 |
416821 |
121402 |
0 |
0 |
T3 |
105137 |
425430 |
0 |
0 |
T4 |
246777 |
216344 |
0 |
0 |
T5 |
198060 |
919367 |
0 |
0 |
T6 |
448314 |
175051 |
0 |
0 |
T7 |
149129 |
10 |
0 |
0 |
T8 |
218250 |
167823 |
0 |
0 |
T9 |
784359 |
542153 |
0 |
0 |
T10 |
350825 |
300082 |
0 |
0 |
Line Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T5,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (8'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
708396835 |
0 |
0 |
T1 |
344452 |
185727 |
0 |
0 |
T2 |
416821 |
254203 |
0 |
0 |
T3 |
105137 |
331621 |
0 |
0 |
T4 |
246777 |
68156 |
0 |
0 |
T5 |
198060 |
309939 |
0 |
0 |
T6 |
448314 |
296272 |
0 |
0 |
T7 |
149129 |
7591 |
0 |
0 |
T8 |
218250 |
112921 |
0 |
0 |
T9 |
784359 |
594086 |
0 |
0 |
T10 |
350825 |
699275 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
344452 |
344446 |
0 |
0 |
T2 |
416821 |
416816 |
0 |
0 |
T3 |
105137 |
105136 |
0 |
0 |
T4 |
246777 |
246770 |
0 |
0 |
T5 |
198060 |
198051 |
0 |
0 |
T6 |
448314 |
448305 |
0 |
0 |
T7 |
149129 |
149062 |
0 |
0 |
T8 |
218250 |
218240 |
0 |
0 |
T9 |
784359 |
784345 |
0 |
0 |
T10 |
350825 |
350817 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
344452 |
344446 |
0 |
0 |
T2 |
416821 |
416816 |
0 |
0 |
T3 |
105137 |
105136 |
0 |
0 |
T4 |
246777 |
246770 |
0 |
0 |
T5 |
198060 |
198051 |
0 |
0 |
T6 |
448314 |
448305 |
0 |
0 |
T7 |
149129 |
149062 |
0 |
0 |
T8 |
218250 |
218240 |
0 |
0 |
T9 |
784359 |
784345 |
0 |
0 |
T10 |
350825 |
350817 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
344452 |
344446 |
0 |
0 |
T2 |
416821 |
416816 |
0 |
0 |
T3 |
105137 |
105136 |
0 |
0 |
T4 |
246777 |
246770 |
0 |
0 |
T5 |
198060 |
198051 |
0 |
0 |
T6 |
448314 |
448305 |
0 |
0 |
T7 |
149129 |
149062 |
0 |
0 |
T8 |
218250 |
218240 |
0 |
0 |
T9 |
784359 |
784345 |
0 |
0 |
T10 |
350825 |
350817 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
708396835 |
0 |
0 |
T1 |
344452 |
185727 |
0 |
0 |
T2 |
416821 |
254203 |
0 |
0 |
T3 |
105137 |
331621 |
0 |
0 |
T4 |
246777 |
68156 |
0 |
0 |
T5 |
198060 |
309939 |
0 |
0 |
T6 |
448314 |
296272 |
0 |
0 |
T7 |
149129 |
7591 |
0 |
0 |
T8 |
218250 |
112921 |
0 |
0 |
T9 |
784359 |
594086 |
0 |
0 |
T10 |
350825 |
699275 |
0 |
0 |