Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14092059	0	0
ctrl_rd_A	2147483647	213091	0	0
intr_enable_rd_A	2147483647	188397	0	0
ovrd_rd_A	2147483647	212957	0	0
timeout_ctrl_rd_A	2147483647	212409	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14092059	0	0
T5	198060	80088	0	0
T6	448314	0	0	0
T7	149129	0	0	0
T8	218250	56066	0	0
T9	784359	113402	0	0
T10	350825	135815	0	0
T15	0	250423	0	0
T23	0	68828	0	0
T24	0	58689	0	0
T25	0	37357	0	0
T26	0	47697	0	0
T27	0	57617	0	0
T28	25022	0	0	0
T29	331801	0	0	0
T30	147793	0	0	0
T31	279336	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	213091	0	0
T8	218250	6233	0	0
T9	784359	12703	0	0
T10	350825	0	0	0
T11	562140	0	0	0
T15	0	18187	0	0
T26	0	5402	0	0
T28	25022	0	0	0
T29	331801	0	0	0
T30	147793	0	0	0
T31	279336	0	0	0
T32	390481	0	0	0
T33	50053	0	0	0
T108	0	7844	0	0
T117	0	3229	0	0
T118	0	16743	0	0
T119	0	8323	0	0
T120	0	5977	0	0
T121	0	3200	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	188397	0	0
T8	218250	5512	0	0
T9	784359	11662	0	0
T10	350825	0	0	0
T11	562140	0	0	0
T15	0	15776	0	0
T26	0	4465	0	0
T28	25022	0	0	0
T29	331801	0	0	0
T30	147793	0	0	0
T31	279336	0	0	0
T32	390481	0	0	0
T33	50053	0	0	0
T117	0	2742	0	0
T118	0	15605	0	0
T119	0	7223	0	0
T122	0	43	0	0
T123	0	22	0	0
T124	0	32	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	212957	0	0
T8	218250	6242	0	0
T9	784359	13391	0	0
T10	350825	0	0	0
T11	562140	0	0	0
T15	0	18098	0	0
T26	0	5120	0	0
T28	25022	0	0	0
T29	331801	0	0	0
T30	147793	0	0	0
T31	279336	0	0	0
T32	390481	0	0	0
T33	50053	0	0	0
T108	0	7832	0	0
T117	0	3034	0	0
T118	0	17296	0	0
T119	0	8237	0	0
T120	0	6790	0	0
T121	0	3172	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	212409	0	0
T8	218250	5771	0	0
T9	784359	12769	0	0
T10	350825	0	0	0
T11	562140	0	0	0
T15	0	18148	0	0
T26	0	5314	0	0
T28	25022	0	0	0
T29	331801	0	0	0
T30	147793	0	0	0
T31	279336	0	0	0
T32	390481	0	0	0
T33	50053	0	0	0
T108	0	8037	0	0
T117	0	3369	0	0
T118	0	16976	0	0
T119	0	8339	0	0
T120	0	5932	0	0
T121	0	3213	0	0