Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	16385084	0	0
ctrl_rd_A	2147483647	294742	0	0
intr_enable_rd_A	2147483647	260901	0	0
ovrd_rd_A	2147483647	295031	0	0
timeout_ctrl_rd_A	2147483647	292221	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16385084	0	0
T9	121954	480657	0	0
T10	651632	0	0	0
T11	38411	0	0	0
T17	0	170411	0	0
T23	0	327831	0	0
T25	0	101147	0	0
T33	11652	0	0	0
T35	0	257402	0	0
T36	0	92221	0	0
T37	0	15221	0	0
T38	0	91524	0	0
T39	0	199296	0	0
T40	0	489688	0	0
T41	16374	0	0	0
T42	675224	0	0	0
T43	187674	0	0	0
T44	901115	0	0	0
T45	193173	0	0	0
T46	171045	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	294742	0	0
T17	571604	9290	0	0
T18	222810	0	0	0
T19	564159	0	0	0
T21	839425	0	0	0
T24	30209	0	0	0
T37	0	1644	0	0
T40	0	25286	0	0
T63	0	13762	0	0
T64	0	3124	0	0
T116	0	8252	0	0
T117	0	6467	0	0
T118	0	12579	0	0
T119	0	6452	0	0
T120	0	3638	0	0
T121	143897	0	0	0
T122	787795	0	0	0
T123	465760	0	0	0
T124	660050	0	0	0
T125	238337	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	260901	0	0
T17	571604	7907	0	0
T18	222810	0	0	0
T19	564159	0	0	0
T21	839425	0	0	0
T24	30209	0	0	0
T37	0	1202	0	0
T40	0	22175	0	0
T63	0	12345	0	0
T64	0	2871	0	0
T78	0	10	0	0
T116	0	7355	0	0
T117	0	5959	0	0
T118	0	11630	0	0
T119	0	5466	0	0
T121	143897	0	0	0
T122	787795	0	0	0
T123	465760	0	0	0
T124	660050	0	0	0
T125	238337	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	295031	0	0
T17	571604	9145	0	0
T18	222810	0	0	0
T19	564159	0	0	0
T21	839425	0	0	0
T24	30209	0	0	0
T37	0	1751	0	0
T40	0	25739	0	0
T63	0	14064	0	0
T64	0	3177	0	0
T116	0	8261	0	0
T117	0	6819	0	0
T118	0	13116	0	0
T119	0	6498	0	0
T120	0	3677	0	0
T121	143897	0	0	0
T122	787795	0	0	0
T123	465760	0	0	0
T124	660050	0	0	0
T125	238337	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	292221	0	0
T17	571604	9100	0	0
T18	222810	0	0	0
T19	564159	0	0	0
T21	839425	0	0	0
T24	30209	0	0	0
T37	0	1561	0	0
T40	0	25182	0	0
T63	0	13851	0	0
T64	0	3152	0	0
T116	0	8019	0	0
T117	0	6690	0	0
T118	0	12751	0	0
T119	0	6007	0	0
T120	0	3846	0	0
T121	143897	0	0	0
T122	787795	0	0	0
T123	465760	0	0	0
T124	660050	0	0	0
T125	238337	0	0	0