Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.76 83.33 97.96 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_intr_state_tx_watermark.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_state_rx_watermark.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_state_tx_empty.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_fifo_ctrl_rxilvl.wr_en_data_arb 95.24 100.00 85.71 100.00
tb.dut.u_reg.u_fifo_ctrl_txilvl.wr_en_data_arb 95.24 100.00 85.71 100.00
tb.dut.u_reg.u_intr_state_tx_done.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_rx_frame_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_rx_break_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_rx_timeout.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_rx_parity_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_watermark.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_watermark.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_done.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_frame_err.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_break_err.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_timeout.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_parity_err.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_empty.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_tx.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_rx.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_nf.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_slpbk.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_parity_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_parity_odd.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_rxblvl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_nco.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wdata.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_txen.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_txval.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state_tx_watermark.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state_rx_watermark.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state_tx_empty.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_tx_done.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_frame_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_break_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_timeout.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_parity_err.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
110 1 1

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=8,SwAccess=2,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=24,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_watermark.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_watermark.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_done.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_frame_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_break_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_timeout.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_parity_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_empty.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_tx.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_rx.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_nf.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_slpbk.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_parity_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_parity_odd.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_rxblvl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_nco.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_wdata.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb

SCORELINE
95.24 100.00
tb.dut.u_reg.u_fifo_ctrl_rxilvl.wr_en_data_arb

SCORELINE
95.24 100.00
tb.dut.u_reg.u_fifo_ctrl_txilvl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ovrd_txen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ovrd_txval.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Module : prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
95.24 85.71
tb.dut.u_reg.u_fifo_ctrl_rxilvl.wr_en_data_arb

SCORECOND
95.24 85.71
tb.dut.u_reg.u_fifo_ctrl_txilvl.wr_en_data_arb

TotalCoveredPercent
Conditions7685.71
Logical7685.71
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T5,T6 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6
Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_tx_done.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_overflow.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_frame_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_break_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_timeout.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_parity_err.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T4 

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_watermark.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_watermark.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_done.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_frame_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_break_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_timeout.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_parity_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_empty.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_tx.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_rx.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_nf.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_slpbk.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_parity_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_parity_odd.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_txen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_txval.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Cond Coverage for Module : prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_nco.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Cond Coverage for Module : prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_rxblvl.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=2,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_wdata.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Cond Coverage for Module : prim_subreg_arb ( parameter DW=24,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T5,T6 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6
Branch Coverage for Module : prim_subreg_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%