Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	13764156	0	0
ctrl_rd_A	2147483647	328124	0	0
intr_enable_rd_A	2147483647	289360	0	0
ovrd_rd_A	2147483647	325278	0	0
timeout_ctrl_rd_A	2147483647	325589	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13764156	0	0
T13	272377	0	0	0
T15	482245	179296	0	0
T16	0	103934	0	0
T20	50181	0	0	0
T26	0	185828	0	0
T32	0	68780	0	0
T33	0	224969	0	0
T34	0	170055	0	0
T35	0	135099	0	0
T36	0	191958	0	0
T37	0	178078	0	0
T38	0	187009	0	0
T39	199066	0	0	0
T40	333776	0	0	0
T41	140923	0	0	0
T42	109532	0	0	0
T43	120597	0	0	0
T44	295338	0	0	0
T45	319082	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	328124	0	0
T16	405577	10995	0	0
T17	289090	0	0	0
T25	742168	0	0	0
T27	1282	0	0	0
T35	0	14649	0	0
T36	0	11847	0	0
T37	0	7549	0	0
T46	625233	0	0	0
T47	136724	0	0	0
T60	0	4880	0	0
T61	0	14898	0	0
T107	0	8469	0	0
T108	0	19889	0	0
T109	0	7373	0	0
T110	0	3237	0	0
T111	480644	0	0	0
T112	61214	0	0	0
T113	439090	0	0	0
T114	207484	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	289360	0	0
T16	405577	10039	0	0
T17	289090	0	0	0
T25	742168	0	0	0
T27	1282	0	0	0
T35	0	12374	0	0
T36	0	9854	0	0
T37	0	7387	0	0
T46	625233	0	0	0
T47	136724	0	0	0
T60	0	4180	0	0
T61	0	13177	0	0
T107	0	7017	0	0
T108	0	17299	0	0
T109	0	6523	0	0
T111	480644	0	0	0
T112	61214	0	0	0
T113	439090	0	0	0
T114	207484	0	0	0
T115	0	23	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	325278	0	0
T16	405577	10897	0	0
T17	289090	0	0	0
T25	742168	0	0	0
T27	1282	0	0	0
T35	0	14403	0	0
T36	0	11722	0	0
T37	0	7438	0	0
T46	625233	0	0	0
T47	136724	0	0	0
T60	0	4615	0	0
T61	0	14751	0	0
T107	0	8641	0	0
T108	0	19786	0	0
T109	0	7435	0	0
T110	0	3452	0	0
T111	480644	0	0	0
T112	61214	0	0	0
T113	439090	0	0	0
T114	207484	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	325589	0	0
T16	405577	11112	0	0
T17	289090	0	0	0
T25	742168	0	0	0
T27	1282	0	0	0
T35	0	14978	0	0
T36	0	11132	0	0
T37	0	7645	0	0
T46	625233	0	0	0
T47	136724	0	0	0
T60	0	4669	0	0
T61	0	15019	0	0
T107	0	8086	0	0
T108	0	19778	0	0
T109	0	7379	0	0
T110	0	3641	0	0
T111	480644	0	0	0
T112	61214	0	0	0
T113	439090	0	0	0
T114	207484	0	0	0