Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
92.86 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_cgs_wrap[uart_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_cgs_wrap[uart_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[uart_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 1 13 100.00


Variables for Group Instance tl_intg_err_cgs_wrap[uart_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 0 4 100.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 131971879 0 T1 45 T2 617811 T3 4905



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_cmd_err_bits

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 131971653 1 T1 45 T2 617811 T3 4905
values[1] 26 1 T89 2 T90 1 T91 2
values[2] 1 1 T90 1 - - - -
values[3] 102 1 T89 8 T90 5 T91 8



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 131971657 1 T1 45 T2 617811 T3 4905
values[1] 19 1 T89 2 T257 1 T94 1
values[2] 5 1 T89 1 T258 1 T259 1
values[3] 111 1 T89 4 T90 9 T91 8



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 131971549 1 T1 45 T2 617811 T3 4905
auto[TlIntgErrCmd] 108 1 T89 7 T90 6 T91 9
auto[TlIntgErrData] 104 1 T89 7 T90 5 T91 6
auto[TlIntgErrBoth] 118 1 T89 6 T90 9 T91 5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%