Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15785049	0	0
ctrl_rd_A	2147483647	255249	0	0
intr_enable_rd_A	2147483647	224261	0	0
ovrd_rd_A	2147483647	251707	0	0
timeout_ctrl_rd_A	2147483647	255073	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15785049	0	0
T2	212995	79995	0	0
T3	471136	0	0	0
T4	139714	0	0	0
T5	269954	0	0	0
T6	195898	0	0	0
T7	260904	0	0	0
T8	387199	0	0	0
T9	50964	0	0	0
T10	925012	0	0	0
T11	179611	0	0	0
T15	0	217357	0	0
T17	0	230445	0	0
T18	0	250790	0	0
T34	0	409751	0	0
T35	0	461477	0	0
T36	0	117120	0	0
T37	0	23574	0	0
T38	0	177351	0	0
T39	0	93738	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	255249	0	0
T17	954671	26052	0	0
T20	852478	0	0	0
T28	631	0	0	0
T52	0	10855	0	0
T109	0	4461	0	0
T110	0	3652	0	0
T111	0	11266	0	0
T112	0	13035	0	0
T113	0	15747	0	0
T114	0	1880	0	0
T115	0	7987	0	0
T116	0	13509	0	0
T117	529274	0	0	0
T118	501339	0	0	0
T119	245640	0	0	0
T120	44118	0	0	0
T121	25923	0	0	0
T122	9868	0	0	0
T123	580350	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	224261	0	0
T17	954671	23052	0	0
T20	852478	0	0	0
T28	631	0	0	0
T109	0	4150	0	0
T110	0	3380	0	0
T111	0	9512	0	0
T112	0	11494	0	0
T113	0	13827	0	0
T114	0	1821	0	0
T115	0	7093	0	0
T117	529274	0	0	0
T118	501339	0	0	0
T119	245640	0	0	0
T120	44118	0	0	0
T121	25923	0	0	0
T122	9868	0	0	0
T123	580350	0	0	0
T124	0	26	0	0
T125	0	12	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	251707	0	0
T17	954671	26107	0	0
T20	852478	0	0	0
T28	631	0	0	0
T52	0	10691	0	0
T109	0	4363	0	0
T110	0	3659	0	0
T111	0	10717	0	0
T112	0	12840	0	0
T113	0	15765	0	0
T114	0	1855	0	0
T115	0	8607	0	0
T116	0	13445	0	0
T117	529274	0	0	0
T118	501339	0	0	0
T119	245640	0	0	0
T120	44118	0	0	0
T121	25923	0	0	0
T122	9868	0	0	0
T123	580350	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	255073	0	0
T17	954671	26225	0	0
T20	852478	0	0	0
T28	631	0	0	0
T52	0	11258	0	0
T109	0	4668	0	0
T110	0	3690	0	0
T111	0	11120	0	0
T112	0	12990	0	0
T113	0	15781	0	0
T114	0	2051	0	0
T115	0	8101	0	0
T116	0	13459	0	0
T117	529274	0	0	0
T118	501339	0	0	0
T119	245640	0	0	0
T120	44118	0	0	0
T121	25923	0	0	0
T122	9868	0	0	0
T123	580350	0	0	0