Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	71940512	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26688666

1

T1

211

T2

285686

T3

105

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	88089224	1			T1	3068		T2	293532		T3	2847
values[0x0]	4984888	1			T1	81		T2	101248		T3	107
values[0x1]	5555066	1			T1	65		T2	112863		T3	86

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49472968	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

49156210

1

T1

1114

T2

358972

T3

1087

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	361252	1			T1	17		T2	1105		T3	8
valid_sources[0x01]	374008	1			T1	8		T2	1452		T3	12
valid_sources[0x02]	344199	1			T1	13		T2	2310		T3	8
valid_sources[0x03]	384210	1			T1	10		T2	2519		T3	13
valid_sources[0x04]	356860	1			T1	15		T2	2494		T3	20
valid_sources[0x05]	452984	1			T1	17		T2	1841		T3	8
valid_sources[0x06]	358634	1			T1	13		T2	2534		T3	17
valid_sources[0x07]	362368	1			T1	8		T2	2627		T3	15
valid_sources[0x08]	432873	1			T1	19		T2	1975		T3	17
valid_sources[0x09]	367737	1			T1	7		T2	1631		T3	5
valid_sources[0x0a]	395530	1			T1	12		T2	1804		T3	8
valid_sources[0x0b]	523942	1			T1	19		T2	2506		T3	10
valid_sources[0x0c]	350874	1			T1	16		T2	2968		T3	13
valid_sources[0x0d]	393849	1			T1	18		T2	1851		T3	15
valid_sources[0x0e]	360537	1			T1	15		T2	1286		T3	7
valid_sources[0x0f]	372394	1			T1	6		T2	3158		T3	11
valid_sources[0x10]	417613	1			T1	18		T2	1906		T3	9
valid_sources[0x11]	359541	1			T1	7		T2	2156		T3	11
valid_sources[0x12]	596644	1			T1	9		T2	2150		T3	2
valid_sources[0x13]	371143	1			T1	10		T2	1613		T3	4
valid_sources[0x14]	363656	1			T1	14		T2	1972		T3	17
valid_sources[0x15]	430092	1			T1	16		T2	1876		T3	9
valid_sources[0x16]	385975	1			T1	10		T2	1570		T3	13
valid_sources[0x17]	394999	1			T1	11		T2	1296		T3	1
valid_sources[0x18]	380864	1			T1	9		T2	1759		T3	10
valid_sources[0x19]	377187	1			T1	12		T2	1793		T3	15
valid_sources[0x1a]	363604	1			T1	15		T2	1817		T3	23
valid_sources[0x1b]	356570	1			T1	17		T2	2188		T3	17
valid_sources[0x1c]	382153	1			T1	12		T2	1047		T3	15
valid_sources[0x1d]	352542	1			T1	11		T2	1340		T3	12
valid_sources[0x1e]	408899	1			T1	19		T2	1951		T4	8
valid_sources[0x1f]	365301	1			T1	6		T2	4411		T3	8
valid_sources[0x20]	387146	1			T1	8		T2	1063		T3	13
valid_sources[0x21]	365953	1			T1	9		T2	1446		T3	9
valid_sources[0x22]	360300	1			T1	11		T2	2150		T3	26
valid_sources[0x23]	359401	1			T1	15		T2	1655		T3	9
valid_sources[0x24]	375494	1			T1	10		T2	1909		T3	15
valid_sources[0x25]	782954	1			T1	14		T2	2130		T3	8
valid_sources[0x26]	364044	1			T1	5		T2	1999		T3	7
valid_sources[0x27]	362782	1			T1	12		T2	1346		T3	12
valid_sources[0x28]	346071	1			T1	12		T2	1143		T3	27
valid_sources[0x29]	375423	1			T1	16		T2	2320		T3	14
valid_sources[0x2a]	387571	1			T1	12		T2	2065		T3	8
valid_sources[0x2b]	435407	1			T1	13		T2	1894		T3	10
valid_sources[0x2c]	352450	1			T1	11		T2	1432		T3	14
valid_sources[0x2d]	366898	1			T1	15		T2	2290		T3	15
valid_sources[0x2e]	351762	1			T1	24		T2	2106		T3	16
valid_sources[0x2f]	388323	1			T1	10		T2	2235		T3	5
valid_sources[0x30]	378463	1			T1	13		T2	1656		T3	22
valid_sources[0x31]	344233	1			T1	10		T2	1827		T3	21
valid_sources[0x32]	386816	1			T1	17		T2	1418		T3	9
valid_sources[0x33]	391907	1			T1	20		T2	2853		T3	15
valid_sources[0x34]	358933	1			T1	10		T2	1854		T3	11
valid_sources[0x35]	382638	1			T1	15		T2	3307		T3	11
valid_sources[0x36]	380410	1			T1	20		T2	1528		T3	5
valid_sources[0x37]	351247	1			T1	15		T2	1395		T3	16
valid_sources[0x38]	346034	1			T1	19		T2	2144		T3	9
valid_sources[0x39]	369561	1			T1	10		T2	936		T3	13
valid_sources[0x3a]	353508	1			T1	10		T2	1781		T3	9
valid_sources[0x3b]	366793	1			T1	7		T2	2760		T3	1
valid_sources[0x3c]	368892	1			T1	6		T2	1719		T3	14
valid_sources[0x3d]	365187	1			T1	12		T2	1735		T3	9
valid_sources[0x3e]	407805	1			T1	14		T2	2325		T3	4
valid_sources[0x3f]	357999	1			T1	6		T2	1095		T3	6
valid_sources[0x40]	358592	1			T1	13		T2	1864		T3	21
valid_sources[0x41]	415062	1			T1	14		T2	1574		T3	3
valid_sources[0x42]	353948	1			T1	10		T2	2286		T3	13
valid_sources[0x43]	369631	1			T1	5		T2	1523		T3	8
valid_sources[0x44]	458502	1			T1	14		T2	1488		T3	22
valid_sources[0x45]	372793	1			T1	18		T2	1845		T3	19
valid_sources[0x46]	366684	1			T1	18		T2	1434		T3	21
valid_sources[0x47]	370487	1			T1	16		T2	1956		T3	12
valid_sources[0x48]	389451	1			T1	11		T2	1670		T3	6
valid_sources[0x49]	419938	1			T1	10		T2	2514		T3	24
valid_sources[0x4a]	363031	1			T1	21		T2	3704		T3	8
valid_sources[0x4b]	374446	1			T1	8		T2	1436		T3	2
valid_sources[0x4c]	397409	1			T1	15		T2	3822		T3	10
valid_sources[0x4d]	385226	1			T1	23		T2	2385		T3	9
valid_sources[0x4e]	434343	1			T1	11		T2	1660		T3	10
valid_sources[0x4f]	367651	1			T1	14		T2	2001		T3	11
valid_sources[0x50]	463915	1			T1	16		T2	1857		T3	16
valid_sources[0x51]	371081	1			T1	13		T2	1381		T3	7
valid_sources[0x52]	359488	1			T1	10		T2	1967		T3	9
valid_sources[0x53]	367150	1			T1	9		T2	2601		T3	14
valid_sources[0x54]	363634	1			T1	10		T2	2469		T3	4
valid_sources[0x55]	355687	1			T1	14		T2	1709		T3	25
valid_sources[0x56]	357217	1			T1	22		T2	3755		T3	6
valid_sources[0x57]	345421	1			T1	11		T2	1842		T3	11
valid_sources[0x58]	378765	1			T1	7		T2	2436		T3	17
valid_sources[0x59]	377943	1			T1	6		T2	1916		T3	6
valid_sources[0x5a]	381753	1			T1	9		T2	1938		T3	4
valid_sources[0x5b]	386708	1			T1	13		T2	2439		T3	32
valid_sources[0x5c]	483154	1			T1	15		T2	1660		T3	11
valid_sources[0x5d]	467760	1			T1	12		T2	2488		T3	12
valid_sources[0x5e]	369464	1			T1	13		T2	1487		T3	9
valid_sources[0x5f]	344829	1			T1	19		T2	1032		T3	8
valid_sources[0x60]	368203	1			T1	16		T2	2516		T3	7
valid_sources[0x61]	392842	1			T1	12		T2	1110		T3	2
valid_sources[0x62]	440313	1			T1	22		T2	1299		T3	10
valid_sources[0x63]	380169	1			T1	6		T2	1707		T3	5
valid_sources[0x64]	358424	1			T1	10		T2	1248		T3	19
valid_sources[0x65]	379854	1			T1	14		T2	1770		T3	5
valid_sources[0x66]	368697	1			T1	12		T2	2064		T3	22
valid_sources[0x67]	371860	1			T1	11		T2	2505		T3	9
valid_sources[0x68]	366020	1			T1	16		T2	2440		T3	14
valid_sources[0x69]	354502	1			T1	5		T2	1386		T3	18
valid_sources[0x6a]	357117	1			T1	17		T2	1513		T3	16
valid_sources[0x6b]	370202	1			T1	10		T2	1697		T3	13
valid_sources[0x6c]	361045	1			T1	7		T2	1655		T3	2
valid_sources[0x6d]	361341	1			T1	13		T2	3129		T3	3
valid_sources[0x6e]	344900	1			T1	12		T2	1790		T3	10
valid_sources[0x6f]	342758	1			T1	9		T2	2802		T3	13
valid_sources[0x70]	365792	1			T1	7		T2	1533		T3	15
valid_sources[0x71]	388057	1			T1	11		T2	3658		T3	22
valid_sources[0x72]	383273	1			T1	18		T2	2493		T3	15
valid_sources[0x73]	425673	1			T1	14		T2	1918		T3	7
valid_sources[0x74]	355403	1			T1	18		T2	1279		T3	20
valid_sources[0x75]	377430	1			T1	12		T2	2999		T3	11
valid_sources[0x76]	434541	1			T1	14		T2	2668		T3	12
valid_sources[0x77]	340566	1			T1	19		T2	1369		T3	7
valid_sources[0x78]	354775	1			T1	11		T2	2016		T3	10
valid_sources[0x79]	356536	1			T1	9		T2	1733		T3	23
valid_sources[0x7a]	417410	1			T1	11		T2	1121		T3	12
valid_sources[0x7b]	375199	1			T1	14		T2	3076		T3	16
valid_sources[0x7c]	353988	1			T1	10		T2	1972		T3	18
valid_sources[0x7d]	356005	1			T1	15		T2	1674		T3	22
valid_sources[0x7e]	378061	1			T1	9		T2	1178		T3	6
valid_sources[0x7f]	365688	1			T1	10		T2	899		T3	3
valid_sources[0x80]	412736	1			T1	20		T2	1882		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17326895

1

T1

147

T2

90833

T3

44

values[0x0]

all_enables

biggest_size

4710150

1

T1

43

T2

97549

T3

46

values[0x1]

all_enables

biggest_size

4651621

1

T1

21

T2

97304

T3

15