Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15261921	0	0
ctrl_rd_A	2147483647	371684	0	0
intr_enable_rd_A	2147483647	328462	0	0
ovrd_rd_A	2147483647	368993	0	0
timeout_ctrl_rd_A	2147483647	369598	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15261921	0	0
T2	106717	311143	0	0
T3	197138	0	0	0
T4	853031	0	0	0
T5	546121	0	0	0
T6	242968	0	0	0
T7	172032	0	0	0
T8	332453	0	0	0
T9	311287	127535	0	0
T10	358035	80663	0	0
T12	0	45766	0	0
T23	0	76257	0	0
T24	0	105775	0	0
T25	0	119644	0	0
T26	0	398370	0	0
T27	0	55816	0	0
T28	0	157270	0	0
T29	320648	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	371684	0	0
T2	106717	16003	0	0
T3	197138	0	0	0
T4	853031	0	0	0
T5	546121	0	0	0
T6	242968	0	0	0
T7	172032	0	0	0
T8	332453	0	0	0
T9	311287	0	0	0
T10	358035	8809	0	0
T23	0	8591	0	0
T24	0	11755	0	0
T25	0	12558	0	0
T27	0	5937	0	0
T29	320648	0	0	0
T42	0	12893	0	0
T101	0	10219	0	0
T102	0	6128	0	0
T103	0	1285	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	328462	0	0
T2	106717	14731	0	0
T3	197138	0	0	0
T4	853031	0	0	0
T5	546121	0	0	0
T6	242968	0	0	0
T7	172032	0	0	0
T8	332453	0	0	0
T9	311287	0	0	0
T10	358035	7788	0	0
T23	0	7442	0	0
T24	0	9737	0	0
T25	0	10854	0	0
T27	0	5409	0	0
T29	320648	0	0	0
T42	0	11125	0	0
T101	0	8669	0	0
T102	0	5495	0	0
T104	0	12	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	368993	0	0
T2	106717	16044	0	0
T3	197138	0	0	0
T4	853031	0	0	0
T5	546121	0	0	0
T6	242968	0	0	0
T7	172032	0	0	0
T8	332453	0	0	0
T9	311287	0	0	0
T10	358035	9152	0	0
T23	0	8303	0	0
T24	0	11458	0	0
T25	0	12967	0	0
T27	0	6124	0	0
T29	320648	0	0	0
T42	0	13035	0	0
T101	0	10061	0	0
T102	0	6107	0	0
T103	0	1211	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	369598	0	0
T2	106717	16121	0	0
T3	197138	0	0	0
T4	853031	0	0	0
T5	546121	0	0	0
T6	242968	0	0	0
T7	172032	0	0	0
T8	332453	0	0	0
T9	311287	0	0	0
T10	358035	9171	0	0
T23	0	9297	0	0
T24	0	11193	0	0
T25	0	12327	0	0
T27	0	6243	0	0
T29	320648	0	0	0
T42	0	12926	0	0
T101	0	9573	0	0
T102	0	6222	0	0
T103	0	1242	0	0