Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 78523023 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 28657558 1 T1 360 T2 62 T3 24



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 98112027 1 T1 530 T2 46 T3 10
values[0x0] 4289134 1 T1 181 T2 47 T3 26
values[0x1] 4779420 1 T1 183 T2 60 T3 19



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 54425024 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 52755557 1 T1 443 T2 77 T3 25



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 411050 1 T6 8 T7 5 T9 152
valid_sources[0x01] 419066 1 T1 4 T6 1 T7 1
valid_sources[0x02] 417229 1 T6 3 T7 4 T9 53
valid_sources[0x03] 382061 1 T1 20 T6 2 T7 4
valid_sources[0x04] 437875 1 T2 1 T6 6 T7 12
valid_sources[0x05] 413573 1 T6 5 T7 9 T9 66
valid_sources[0x06] 386756 1 T6 9 T9 116 T10 8
valid_sources[0x07] 408326 1 T6 8 T7 8 T9 65
valid_sources[0x08] 447569 1 T4 1 T6 9 T7 7
valid_sources[0x09] 678228 1 T6 9 T9 25 T10 1148
valid_sources[0x0a] 380649 1 T6 2 T7 6 T9 95
valid_sources[0x0b] 493681 1 T1 9 T2 1 T6 4
valid_sources[0x0c] 424940 1 T6 5 T7 3 T9 67
valid_sources[0x0d] 473871 1 T6 8 T7 12 T9 92
valid_sources[0x0e] 445567 1 T6 6 T9 121 T10 3831
valid_sources[0x0f] 395177 1 T2 1 T6 5 T7 11
valid_sources[0x10] 412927 1 T1 2 T6 2 T9 53
valid_sources[0x11] 447687 1 T1 3 T6 5 T7 1
valid_sources[0x12] 510094 1 T1 33 T6 4 T7 8
valid_sources[0x13] 389089 1 T1 3 T3 1 T6 4
valid_sources[0x14] 425017 1 T1 9 T6 3 T7 3
valid_sources[0x15] 385379 1 T6 5 T9 113 T10 2567
valid_sources[0x16] 448738 1 T2 1 T3 4 T5 4617
valid_sources[0x17] 410115 1 T1 13 T6 3 T7 6
valid_sources[0x18] 415098 1 T1 17 T2 1 T6 9
valid_sources[0x19] 422477 1 T1 24 T2 4 T6 5
valid_sources[0x1a] 389106 1 T6 5 T9 59 T10 301
valid_sources[0x1b] 370261 1 T1 6 T5 569 T6 5
valid_sources[0x1c] 387224 1 T2 1 T3 1 T6 8
valid_sources[0x1d] 406141 1 T2 1 T6 3 T7 1
valid_sources[0x1e] 384923 1 T2 2 T6 9 T7 14
valid_sources[0x1f] 402282 1 T6 2 T7 1 T9 95
valid_sources[0x20] 458332 1 T2 4 T6 5 T9 70
valid_sources[0x21] 375438 1 T1 10 T6 5 T7 6
valid_sources[0x22] 400382 1 T6 4 T9 80 T10 7062
valid_sources[0x23] 386580 1 T3 1 T6 6 T7 2
valid_sources[0x24] 466938 1 T2 3 T6 5 T7 1
valid_sources[0x25] 393762 1 T5 3 T6 6 T7 1
valid_sources[0x26] 412587 1 T6 5 T7 16 T9 75
valid_sources[0x27] 451028 1 T6 11 T7 6 T9 78
valid_sources[0x28] 449971 1 T2 7 T6 6 T7 8
valid_sources[0x29] 379017 1 T6 5 T7 14 T9 68
valid_sources[0x2a] 420934 1 T1 3 T2 1 T9 46
valid_sources[0x2b] 441833 1 T1 4 T6 4 T9 68
valid_sources[0x2c] 449433 1 T6 8 T7 6 T9 64
valid_sources[0x2d] 389328 1 T2 1 T6 3 T7 8
valid_sources[0x2e] 416876 1 T1 11 T6 5 T7 4
valid_sources[0x2f] 389336 1 T6 5 T7 3 T9 94
valid_sources[0x30] 417257 1 T6 5 T7 12 T9 51
valid_sources[0x31] 470184 1 T6 3 T7 2 T9 54
valid_sources[0x32] 383816 1 T5 15 T6 4 T7 7
valid_sources[0x33] 403088 1 T5 547 T6 8 T7 22
valid_sources[0x34] 411937 1 T5 3570 T6 2 T7 17
valid_sources[0x35] 404540 1 T2 6 T3 1 T6 3
valid_sources[0x36] 477303 1 T1 6 T6 10 T8 7474
valid_sources[0x37] 382487 1 T6 2 T9 94 T10 15
valid_sources[0x38] 456312 1 T6 5 T9 59 T10 1647
valid_sources[0x39] 399881 1 T1 35 T6 9 T7 7
valid_sources[0x3a] 385106 1 T6 4 T9 128 T10 44
valid_sources[0x3b] 382906 1 T1 8 T3 13 T6 5
valid_sources[0x3c] 408722 1 T6 6 T7 5 T9 84
valid_sources[0x3d] 414645 1 T3 2 T6 8 T7 12
valid_sources[0x3e] 392281 1 T2 5 T4 1190 T6 9
valid_sources[0x3f] 403865 1 T6 9 T9 73 T10 5164
valid_sources[0x40] 469135 1 T2 5 T6 3 T7 6
valid_sources[0x41] 452435 1 T6 10 T7 7 T9 114
valid_sources[0x42] 456321 1 T6 7 T7 5 T9 87
valid_sources[0x43] 434402 1 T6 5 T7 5 T9 64
valid_sources[0x44] 384036 1 T2 6 T6 3 T9 120
valid_sources[0x45] 386701 1 T6 5 T7 3 T9 107
valid_sources[0x46] 433661 1 T2 3 T6 5 T7 9
valid_sources[0x47] 421990 1 T6 7 T7 7 T9 53
valid_sources[0x48] 483828 1 T6 3 T9 35 T10 244
valid_sources[0x49] 388666 1 T6 3 T7 11 T9 35
valid_sources[0x4a] 397275 1 T2 3 T6 3 T9 109
valid_sources[0x4b] 411045 1 T1 1 T6 5 T7 16
valid_sources[0x4c] 385048 1 T6 4 T9 66 T10 5803
valid_sources[0x4d] 405208 1 T2 2 T6 3 T7 6
valid_sources[0x4e] 402080 1 T6 5 T7 1 T9 117
valid_sources[0x4f] 464726 1 T1 17 T6 12 T7 10
valid_sources[0x50] 399566 1 T2 1 T3 8 T6 3
valid_sources[0x51] 413808 1 T6 4 T9 54 T10 2
valid_sources[0x52] 403401 1 T6 6 T9 34 T10 1
valid_sources[0x53] 414697 1 T2 1 T6 7 T7 3
valid_sources[0x54] 429081 1 T6 6 T7 3 T9 76
valid_sources[0x55] 375874 1 T2 3 T6 4 T7 1
valid_sources[0x56] 390733 1 T2 3 T6 7 T7 5
valid_sources[0x57] 409370 1 T5 6 T6 7 T7 1
valid_sources[0x58] 391105 1 T1 2 T2 1 T6 4
valid_sources[0x59] 393758 1 T6 5 T7 4 T9 76
valid_sources[0x5a] 417389 1 T2 5 T6 7 T7 2
valid_sources[0x5b] 386738 1 T6 1 T9 59 T10 5428
valid_sources[0x5c] 394140 1 T6 6 T9 89 T10 6
valid_sources[0x5d] 390899 1 T6 4 T7 3 T9 99
valid_sources[0x5e] 401782 1 T2 1 T6 6 T9 70
valid_sources[0x5f] 399502 1 T6 2 T7 13 T9 39
valid_sources[0x60] 442818 1 T6 8 T7 4 T9 49
valid_sources[0x61] 410803 1 T5 3705 T6 6 T7 6
valid_sources[0x62] 412767 1 T1 1 T6 4 T7 2
valid_sources[0x63] 407849 1 T1 18 T6 6 T7 5
valid_sources[0x64] 462295 1 T6 4 T7 8 T9 66
valid_sources[0x65] 393893 1 T2 3 T6 7 T7 5
valid_sources[0x66] 383724 1 T9 68 T10 2469 T41 748
valid_sources[0x67] 403694 1 T6 4 T9 81 T10 6209
valid_sources[0x68] 388073 1 T2 4 T6 2 T7 12
valid_sources[0x69] 422999 1 T1 25 T2 2 T6 8
valid_sources[0x6a] 399181 1 T6 3 T7 1 T9 78
valid_sources[0x6b] 469391 1 T1 1 T5 286 T6 3
valid_sources[0x6c] 526335 1 T6 7 T7 1 T9 91
valid_sources[0x6d] 385877 1 T2 1 T6 4 T7 9
valid_sources[0x6e] 370784 1 T1 38 T6 3 T7 5
valid_sources[0x6f] 388937 1 T6 3 T7 7 T9 105
valid_sources[0x70] 450989 1 T1 28 T2 1 T6 6
valid_sources[0x71] 386133 1 T1 1 T6 5 T9 121
valid_sources[0x72] 416619 1 T1 4 T6 7 T7 1
valid_sources[0x73] 420995 1 T6 3 T7 4 T9 25
valid_sources[0x74] 465618 1 T1 8 T6 1 T7 1
valid_sources[0x75] 401469 1 T6 3 T9 121 T10 94
valid_sources[0x76] 429900 1 T5 2517 T6 5 T7 3
valid_sources[0x77] 405633 1 T6 3 T9 129 T10 74
valid_sources[0x78] 399433 1 T1 9 T6 5 T9 56
valid_sources[0x79] 493802 1 T6 4 T7 2 T9 80
valid_sources[0x7a] 398579 1 T6 9 T9 119 T10 7
valid_sources[0x7b] 461148 1 T3 7 T5 1 T6 6
valid_sources[0x7c] 392287 1 T6 3 T9 76 T10 49
valid_sources[0x7d] 383382 1 T1 13 T6 3 T9 52
valid_sources[0x7e] 529481 1 T6 7 T7 4 T9 65
valid_sources[0x7f] 391703 1 T2 2 T6 4 T7 14
valid_sources[0x80] 428114 1 T1 8 T6 3 T9 73



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 20670463 1 T1 254 T2 21 T3 7
values[0x0] all_enables biggest_size 4024631 1 T1 63 T2 20 T3 12
values[0x1] all_enables biggest_size 3962464 1 T1 43 T2 21 T3 5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%