Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	13136171	0	0
ctrl_rd_A	2147483647	207611	0	0
intr_enable_rd_A	2147483647	185852	0	0
ovrd_rd_A	2147483647	206580	0	0
timeout_ctrl_rd_A	2147483647	207513	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13136171	0	0
T12	240956	98499	0	0
T14	0	162692	0	0
T15	0	84045	0	0
T17	185936	79244	0	0
T18	0	50156	0	0
T21	194705	67254	0	0
T22	268783	0	0	0
T23	0	239269	0	0
T25	323056	125653	0	0
T34	0	188138	0	0
T35	0	79682	0	0
T36	221345	0	0	0
T37	855997	0	0	0
T38	237805	0	0	0
T39	145226	0	0	0
T40	210458	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	207611	0	0
T18	259734	6107	0	0
T19	816399	0	0	0
T23	947523	0	0	0
T24	0	13091	0	0
T27	1138	0	0	0
T28	837	0	0	0
T35	0	8448	0	0
T43	479831	0	0	0
T44	314715	0	0	0
T45	782464	0	0	0
T46	107365	0	0	0
T47	894031	0	0	0
T99	0	15387	0	0
T100	0	9429	0	0
T101	0	6421	0	0
T102	0	4303	0	0
T103	0	3364	0	0
T104	0	16350	0	0
T105	0	1825	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	185852	0	0
T18	259734	5120	0	0
T19	816399	0	0	0
T23	947523	0	0	0
T24	0	11378	0	0
T27	1138	0	0	0
T28	837	0	0	0
T35	0	7979	0	0
T43	479831	0	0	0
T44	314715	0	0	0
T45	782464	0	0	0
T46	107365	0	0	0
T47	894031	0	0	0
T99	0	14040	0	0
T100	0	8851	0	0
T101	0	5774	0	0
T102	0	3577	0	0
T103	0	2737	0	0
T104	0	14744	0	0
T105	0	1896	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	206580	0	0
T18	259734	5778	0	0
T19	816399	0	0	0
T23	947523	0	0	0
T24	0	12905	0	0
T27	1138	0	0	0
T28	837	0	0	0
T35	0	8586	0	0
T43	479831	0	0	0
T44	314715	0	0	0
T45	782464	0	0	0
T46	107365	0	0	0
T47	894031	0	0	0
T99	0	15333	0	0
T100	0	9585	0	0
T101	0	6635	0	0
T102	0	4337	0	0
T103	0	3267	0	0
T104	0	16081	0	0
T105	0	2248	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	207513	0	0
T18	259734	5726	0	0
T19	816399	0	0	0
T23	947523	0	0	0
T24	0	12913	0	0
T27	1138	0	0	0
T28	837	0	0	0
T35	0	9323	0	0
T43	479831	0	0	0
T44	314715	0	0	0
T45	782464	0	0	0
T46	107365	0	0	0
T47	894031	0	0	0
T99	0	15157	0	0
T100	0	9579	0	0
T101	0	6285	0	0
T102	0	4177	0	0
T103	0	3414	0	0
T104	0	16478	0	0
T105	0	2224	0	0