Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	73974430	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28752772

1

T1

119806

T2

99

T3

129

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	92794121	1			T1	257341		T2	105		T3	1137
values[0x0]	4696510	1			T1	346		T2	104		T3	104
values[0x1]	5236571	1			T1	361		T2	99		T3	107

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51220090	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

51507112

1

T1

150091

T2

136

T3

515

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	421102	1			T1	1044		T2	2		T3	3
valid_sources[0x01]	393544	1			T1	983		T3	4		T7	10
valid_sources[0x02]	445370	1			T1	936		T2	1		T3	2
valid_sources[0x03]	459854	1			T1	981		T2	1		T3	2
valid_sources[0x04]	449712	1			T1	1034		T2	5		T3	5
valid_sources[0x05]	401065	1			T1	1014		T2	7		T3	5
valid_sources[0x06]	415387	1			T1	999		T2	3		T3	10
valid_sources[0x07]	381108	1			T1	1061		T3	4		T7	10
valid_sources[0x08]	441367	1			T1	1046		T3	3		T4	2
valid_sources[0x09]	367892	1			T1	1013		T2	2		T3	8
valid_sources[0x0a]	378943	1			T1	1024		T2	2		T3	4
valid_sources[0x0b]	353132	1			T1	999		T2	2		T3	2
valid_sources[0x0c]	353690	1			T1	950		T3	4		T4	1
valid_sources[0x0d]	380373	1			T1	1035		T3	10		T4	5
valid_sources[0x0e]	368930	1			T1	967		T3	9		T7	10
valid_sources[0x0f]	392311	1			T1	976		T3	4		T7	13
valid_sources[0x10]	373867	1			T1	1050		T3	4		T7	10
valid_sources[0x11]	387068	1			T1	977		T2	1		T3	6
valid_sources[0x12]	384106	1			T1	1041		T3	7		T7	4
valid_sources[0x13]	391748	1			T1	1034		T3	11		T4	2
valid_sources[0x14]	348185	1			T1	994		T2	2		T3	10
valid_sources[0x15]	357358	1			T1	1038		T7	11		T11	26
valid_sources[0x16]	351555	1			T1	1022		T3	2		T7	13
valid_sources[0x17]	413487	1			T1	993		T2	3		T3	8
valid_sources[0x18]	389909	1			T1	989		T2	4		T3	3
valid_sources[0x19]	446621	1			T1	1015		T2	1		T3	5
valid_sources[0x1a]	419335	1			T1	965		T2	3		T3	2
valid_sources[0x1b]	368326	1			T1	1011		T2	2		T3	5
valid_sources[0x1c]	367644	1			T1	961		T2	1		T3	7
valid_sources[0x1d]	382376	1			T1	998		T2	1		T3	6
valid_sources[0x1e]	346469	1			T1	1021		T2	3		T3	4
valid_sources[0x1f]	406253	1			T1	1042		T2	3		T3	4
valid_sources[0x20]	369978	1			T1	961		T2	3		T3	6
valid_sources[0x21]	389753	1			T1	953		T2	2		T3	4
valid_sources[0x22]	364870	1			T1	983		T3	5		T7	11
valid_sources[0x23]	389058	1			T1	1020		T2	4		T3	4
valid_sources[0x24]	456018	1			T1	995		T3	4		T7	9
valid_sources[0x25]	392892	1			T1	1010		T2	1		T3	4
valid_sources[0x26]	347972	1			T1	1014		T2	2		T3	8
valid_sources[0x27]	390685	1			T1	1040		T2	1		T3	6
valid_sources[0x28]	423560	1			T1	998		T2	2		T3	9
valid_sources[0x29]	408178	1			T1	1011		T2	5		T3	6
valid_sources[0x2a]	362312	1			T1	1024		T3	10		T7	12
valid_sources[0x2b]	379645	1			T1	1093		T2	2		T3	2
valid_sources[0x2c]	370027	1			T1	982		T2	4		T3	2
valid_sources[0x2d]	510250	1			T1	1047		T3	8		T4	2
valid_sources[0x2e]	406519	1			T1	923		T2	3		T3	7
valid_sources[0x2f]	390712	1			T1	1004		T2	3		T3	8
valid_sources[0x30]	473879	1			T1	1062		T2	2		T3	7
valid_sources[0x31]	358177	1			T1	1086		T2	5		T3	7
valid_sources[0x32]	399482	1			T1	967		T2	1		T3	4
valid_sources[0x33]	380079	1			T1	1037		T2	2		T3	4
valid_sources[0x34]	384783	1			T1	974		T3	7		T4	11
valid_sources[0x35]	407806	1			T1	1035		T2	1		T3	2
valid_sources[0x36]	373576	1			T1	981		T2	1		T3	7
valid_sources[0x37]	421495	1			T1	937		T2	1		T3	7
valid_sources[0x38]	378604	1			T1	1013		T3	4		T4	1
valid_sources[0x39]	367852	1			T1	954		T2	2		T3	6
valid_sources[0x3a]	392936	1			T1	987		T2	3		T3	3
valid_sources[0x3b]	423193	1			T1	1057		T3	3		T7	9
valid_sources[0x3c]	350053	1			T1	988		T2	1		T3	4
valid_sources[0x3d]	399750	1			T1	1007		T2	2		T3	3
valid_sources[0x3e]	365993	1			T1	992		T2	1		T3	5
valid_sources[0x3f]	373613	1			T1	963		T2	1		T3	4
valid_sources[0x40]	370814	1			T1	946		T3	4		T4	8
valid_sources[0x41]	429482	1			T1	1047		T3	5		T4	1
valid_sources[0x42]	400805	1			T1	1038		T3	4		T7	14
valid_sources[0x43]	374541	1			T1	1019		T2	1		T3	7
valid_sources[0x44]	353907	1			T1	976		T3	10		T7	12
valid_sources[0x45]	372425	1			T1	960		T3	4		T4	1
valid_sources[0x46]	389761	1			T1	964		T3	5		T7	14
valid_sources[0x47]	374241	1			T1	1059		T3	5		T4	4
valid_sources[0x48]	435954	1			T1	1083		T2	2		T3	7
valid_sources[0x49]	372449	1			T1	973		T2	1		T3	7
valid_sources[0x4a]	374179	1			T1	1062		T2	2		T3	6
valid_sources[0x4b]	409217	1			T1	961		T2	1		T3	7
valid_sources[0x4c]	389348	1			T1	978		T2	1		T3	4
valid_sources[0x4d]	375868	1			T1	1055		T2	5		T3	7
valid_sources[0x4e]	452682	1			T1	993		T2	1		T3	13
valid_sources[0x4f]	380760	1			T1	966		T3	8		T4	2
valid_sources[0x50]	393665	1			T1	951		T2	1		T3	6
valid_sources[0x51]	392810	1			T1	970		T2	2		T3	2
valid_sources[0x52]	427186	1			T1	1047		T2	2		T3	5
valid_sources[0x53]	463631	1			T1	1060		T3	5		T4	10
valid_sources[0x54]	373791	1			T1	1036		T3	10		T4	6
valid_sources[0x55]	388603	1			T1	1022		T2	2		T3	5
valid_sources[0x56]	362073	1			T1	992		T3	2		T4	7
valid_sources[0x57]	420924	1			T1	996		T3	8		T7	9
valid_sources[0x58]	372568	1			T1	994		T2	4		T3	4
valid_sources[0x59]	363130	1			T1	1011		T3	7		T7	12
valid_sources[0x5a]	378389	1			T1	996		T2	2		T3	4
valid_sources[0x5b]	491286	1			T1	1062		T3	2		T7	7
valid_sources[0x5c]	429827	1			T1	1003		T3	9		T7	11
valid_sources[0x5d]	464489	1			T1	992		T2	1		T3	5
valid_sources[0x5e]	361248	1			T1	1015		T2	1		T3	7
valid_sources[0x5f]	390335	1			T1	990		T3	6		T4	1
valid_sources[0x60]	371890	1			T1	1041		T3	4		T4	6
valid_sources[0x61]	361171	1			T1	1034		T2	2		T3	7
valid_sources[0x62]	371592	1			T1	1019		T3	1		T4	2
valid_sources[0x63]	377476	1			T1	1036		T2	1		T3	5
valid_sources[0x64]	381322	1			T1	986		T3	4		T4	3
valid_sources[0x65]	512311	1			T1	986		T2	1		T3	2
valid_sources[0x66]	373206	1			T1	1094		T2	3		T3	6
valid_sources[0x67]	377922	1			T1	1038		T2	1		T3	6
valid_sources[0x68]	355956	1			T1	990		T2	2		T3	6
valid_sources[0x69]	387337	1			T1	1078		T3	8		T7	9
valid_sources[0x6a]	376383	1			T1	989		T2	3		T3	7
valid_sources[0x6b]	381312	1			T1	1019		T2	1		T3	6
valid_sources[0x6c]	360004	1			T1	1015		T2	1		T3	6
valid_sources[0x6d]	369674	1			T1	944		T2	4		T3	6
valid_sources[0x6e]	374334	1			T1	926		T3	6		T7	5
valid_sources[0x6f]	434581	1			T1	1022		T2	2		T3	2
valid_sources[0x70]	534961	1			T1	1048		T3	1		T7	10
valid_sources[0x71]	359889	1			T1	975		T3	4		T4	3
valid_sources[0x72]	363073	1			T1	1000		T3	5		T4	5
valid_sources[0x73]	410377	1			T1	1001		T2	2		T3	12
valid_sources[0x74]	525356	1			T1	995		T3	2		T4	2
valid_sources[0x75]	374117	1			T1	1030		T3	7		T7	13
valid_sources[0x76]	351647	1			T1	1053		T2	5		T3	6
valid_sources[0x77]	466952	1			T1	1001		T2	1		T3	7
valid_sources[0x78]	473788	1			T1	1030		T3	3		T4	1
valid_sources[0x79]	391939	1			T1	1009		T2	2		T3	10
valid_sources[0x7a]	383344	1			T1	999		T2	2		T3	6
valid_sources[0x7b]	373685	1			T1	1004		T2	1		T3	9
valid_sources[0x7c]	377229	1			T1	968		T2	2		T3	8
valid_sources[0x7d]	445728	1			T1	1045		T2	2		T3	5
valid_sources[0x7e]	365963	1			T1	986		T3	7		T4	1
valid_sources[0x7f]	399048	1			T1	1091		T2	4		T3	4
valid_sources[0x80]	458094	1			T1	1036		T3	10		T7	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19946053

1

T1

119555

T2

25

T3

62

values[0x0]

all_enables

biggest_size

4435130

1

T1

166

T2

45

T3

37

values[0x1]

all_enables

biggest_size

4371589

1

T1

85

T2

29

T3

30