Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14604133	0	0
ctrl_rd_A	2147483647	241523	0	0
intr_enable_rd_A	2147483647	211504	0	0
ovrd_rd_A	2147483647	238566	0	0
timeout_ctrl_rd_A	2147483647	238837	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14604133	0	0
T14	787918	165970	0	0
T17	456839	156765	0	0
T18	0	55507	0	0
T19	0	311355	0	0
T26	0	153547	0	0
T27	0	124853	0	0
T28	0	276792	0	0
T29	0	154069	0	0
T30	0	114087	0	0
T31	0	125554	0	0
T32	267539	0	0	0
T33	116912	0	0	0
T34	180628	0	0	0
T35	306425	0	0	0
T36	909381	0	0	0
T37	227667	0	0	0
T38	783156	0	0	0
T39	10252	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	241523	0	0
T14	787918	19451	0	0
T17	456839	4612	0	0
T18	0	6455	0	0
T32	267539	0	0	0
T33	116912	0	0	0
T34	180628	0	0	0
T35	306425	0	0	0
T36	909381	0	0	0
T37	227667	0	0	0
T38	783156	0	0	0
T39	10252	0	0	0
T43	0	7447	0	0
T44	0	11674	0	0
T93	0	2146	0	0
T94	0	1553	0	0
T95	0	6340	0	0
T96	0	5750	0	0
T97	0	8662	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	211504	0	0
T14	787918	15845	0	0
T17	456839	3792	0	0
T18	0	5724	0	0
T32	267539	0	0	0
T33	116912	0	0	0
T34	180628	0	0	0
T35	306425	0	0	0
T36	909381	0	0	0
T37	227667	0	0	0
T38	783156	0	0	0
T39	10252	0	0	0
T43	0	6497	0	0
T44	0	10482	0	0
T93	0	1995	0	0
T94	0	1455	0	0
T95	0	5396	0	0
T96	0	5295	0	0
T97	0	7720	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	238566	0	0
T14	787918	18161	0	0
T17	456839	4625	0	0
T18	0	6539	0	0
T32	267539	0	0	0
T33	116912	0	0	0
T34	180628	0	0	0
T35	306425	0	0	0
T36	909381	0	0	0
T37	227667	0	0	0
T38	783156	0	0	0
T39	10252	0	0	0
T43	0	7039	0	0
T44	0	11902	0	0
T93	0	2071	0	0
T94	0	1419	0	0
T95	0	6158	0	0
T96	0	5848	0	0
T97	0	8515	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	238837	0	0
T14	787918	18375	0	0
T17	456839	4589	0	0
T18	0	6551	0	0
T32	267539	0	0	0
T33	116912	0	0	0
T34	180628	0	0	0
T35	306425	0	0	0
T36	909381	0	0	0
T37	227667	0	0	0
T38	783156	0	0	0
T39	10252	0	0	0
T43	0	7204	0	0
T44	0	11773	0	0
T93	0	1971	0	0
T94	0	1587	0	0
T95	0	6081	0	0
T96	0	5776	0	0
T97	0	8743	0	0