SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.uart_core.sync_rx |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.98 | 98.94 | 99.04 | 97.96 | 100.00 | uart_core |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |