Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	16225024	0	0
ctrl_rd_A	2147483647	172846	0	0
intr_enable_rd_A	2147483647	153907	0	0
ovrd_rd_A	2147483647	173314	0	0
timeout_ctrl_rd_A	2147483647	172327	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16225024	0	0
T12	0	248482	0	0
T13	105665	44887	0	0
T14	277162	105844	0	0
T15	348093	0	0	0
T16	217600	53508	0	0
T20	0	129544	0	0
T21	0	63170	0	0
T22	934368	0	0	0
T29	0	57366	0	0
T30	0	81881	0	0
T31	0	319001	0	0
T32	0	88429	0	0
T33	796893	0	0	0
T34	184526	0	0	0
T35	526864	0	0	0
T36	185616	0	0	0
T37	42305	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	172846	0	0
T12	136452	28282	0	0
T16	217600	6006	0	0
T20	102313	0	0	0
T32	0	9262	0	0
T37	42305	0	0	0
T39	278901	0	0	0
T40	182801	0	0	0
T112	0	18195	0	0
T113	0	11022	0	0
T114	0	2808	0	0
T115	0	7690	0	0
T116	0	6354	0	0
T117	0	10416	0	0
T118	0	5695	0	0
T119	751389	0	0	0
T120	839759	0	0	0
T121	135983	0	0	0
T122	152816	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	153907	0	0
T12	136452	24696	0	0
T16	217600	5727	0	0
T20	102313	0	0	0
T32	0	8575	0	0
T37	42305	0	0	0
T39	278901	0	0	0
T40	182801	0	0	0
T112	0	16283	0	0
T113	0	9919	0	0
T114	0	2388	0	0
T115	0	6738	0	0
T116	0	6008	0	0
T117	0	9273	0	0
T118	0	4732	0	0
T119	751389	0	0	0
T120	839759	0	0	0
T121	135983	0	0	0
T122	152816	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	173314	0	0
T12	136452	28376	0	0
T16	217600	6117	0	0
T20	102313	0	0	0
T32	0	9301	0	0
T37	42305	0	0	0
T39	278901	0	0	0
T40	182801	0	0	0
T112	0	18422	0	0
T113	0	11198	0	0
T114	0	3197	0	0
T115	0	7774	0	0
T116	0	6750	0	0
T117	0	10178	0	0
T118	0	5638	0	0
T119	751389	0	0	0
T120	839759	0	0	0
T121	135983	0	0	0
T122	152816	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	172327	0	0
T12	136452	28378	0	0
T16	217600	5825	0	0
T20	102313	0	0	0
T32	0	9382	0	0
T37	42305	0	0	0
T39	278901	0	0	0
T40	182801	0	0	0
T112	0	18670	0	0
T113	0	11254	0	0
T114	0	2840	0	0
T115	0	8029	0	0
T116	0	6683	0	0
T117	0	10095	0	0
T118	0	5400	0	0
T119	751389	0	0	0
T120	839759	0	0	0
T121	135983	0	0	0
T122	152816	0	0	0