Unified Coverage Report :: Module :: uart_tx

Module : uart_tx

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_core.uart_tx	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.uart_core.uart_tx

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.98	98.94	99.04			97.96	100.00	uart_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : uart_tx

	Line No.	Total	Covered	Percent
TOTAL		29	29	100.00
CONT_ASSIGN	32	1	1	100.00
ALWAYS	35	6	6	100.00
ALWAYS	46	7	7	100.00
ALWAYS	58	14	14	100.00
CONT_ASSIGN	77	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	1	1
35	1	1
36	1	1
37	1	1
38	1	1
39	1	1
41	1	1
46	1	1
47	1	1
48	1	1
49	1	1
51	1	1
52	1	1
53	1	1
58	1	1
59	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
77	1	1

---

Cond Coverage for Module : uart_tx

	Total	Covered	Percent
Conditions	13	13	100.00
Logical	13	13	100.00
Non-Logical	0	0
Event	0	0

 LINE       67
 SUB-EXPRESSION (parity_enable ? wr_parity : 1'b1)
                 ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T4

 LINE       68
 EXPRESSION (parity_enable ? 4'd11 : 4'd10)
             ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T4

 LINE       69
 EXPRESSION (tick_baud_q && (bit_cnt_q != 4'b0))
             -----1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       69
 SUB-EXPRESSION (bit_cnt_q != 4'b0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       77
 EXPRESSION (tx_enable ? (bit_cnt_q == 4'b0) : 1'b1)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       77
 SUB-EXPRESSION (bit_cnt_q == 4'b0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Module : uart_tx

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	77	2	2	100.00
IF	35	3	3	100.00
IF	46	2	2	100.00
IF	58	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_tx.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	77	(tx_enable) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	35	if ((!rst_ni))
-2-:	38	if (tick_baud_x16)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	46	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	58	if ((!tx_enable))
-2-:	66	if (wr)
-3-:	68	(parity_enable) ? 
-4-:	69	if ((tick_baud_q && (bit_cnt_q != 4'b0)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Covered	T1,T2,T4
0	1	0	-	Covered	T4,T5,T6
0	0	-	1	Covered	T1,T2,T4
0	0	-	0	Covered	T1,T2,T3