Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14229100	0	0
ctrl_rd_A	2147483647	244990	0	0
intr_enable_rd_A	2147483647	217139	0	0
ovrd_rd_A	2147483647	243367	0	0
timeout_ctrl_rd_A	2147483647	243332	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14229100	0	0
T8	369195	143571	0	0
T9	348138	0	0	0
T10	762326	312952	0	0
T11	140366	0	0	0
T13	0	17065	0	0
T14	0	94817	0	0
T17	0	161693	0	0
T18	0	136629	0	0
T25	805017	0	0	0
T27	0	193418	0	0
T28	0	31954	0	0
T29	0	138485	0	0
T30	0	40330	0	0
T31	103592	0	0	0
T32	432835	0	0	0
T33	336972	0	0	0
T34	141900	0	0	0
T35	280453	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	244990	0	0
T14	347742	4419	0	0
T18	344402	0	0	0
T22	3296	0	0	0
T28	129298	3709	0	0
T29	0	7881	0	0
T37	138468	0	0	0
T38	252598	0	0	0
T90	605516	0	0	0
T91	134047	0	0	0
T99	0	2839	0	0
T100	0	6498	0	0
T101	0	20708	0	0
T102	0	4381	0	0
T103	0	17395	0	0
T104	0	29050	0	0
T105	0	5490	0	0
T106	291560	0	0	0
T107	206470	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	217139	0	0
T14	347742	3494	0	0
T18	344402	0	0	0
T22	3296	0	0	0
T28	129298	3457	0	0
T29	0	7002	0	0
T37	138468	0	0	0
T38	252598	0	0	0
T90	605516	0	0	0
T91	134047	0	0	0
T99	0	2410	0	0
T100	0	5515	0	0
T101	0	17937	0	0
T102	0	3843	0	0
T103	0	15341	0	0
T106	291560	0	0	0
T107	206470	0	0	0
T108	0	38	0	0
T109	0	7	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	243367	0	0
T14	347742	4136	0	0
T18	344402	0	0	0
T22	3296	0	0	0
T28	129298	3782	0	0
T29	0	7966	0	0
T37	138468	0	0	0
T38	252598	0	0	0
T90	605516	0	0	0
T91	134047	0	0	0
T99	0	2683	0	0
T100	0	6392	0	0
T101	0	19928	0	0
T102	0	4588	0	0
T103	0	17339	0	0
T104	0	29237	0	0
T105	0	5406	0	0
T106	291560	0	0	0
T107	206470	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	243332	0	0
T14	347742	4141	0	0
T18	344402	0	0	0
T22	3296	0	0	0
T28	129298	3663	0	0
T29	0	7667	0	0
T37	138468	0	0	0
T38	252598	0	0	0
T90	605516	0	0	0
T91	134047	0	0	0
T99	0	2763	0	0
T100	0	5930	0	0
T101	0	19959	0	0
T102	0	4525	0	0
T103	0	16990	0	0
T104	0	29265	0	0
T105	0	5009	0	0
T106	291560	0	0	0
T107	206470	0	0	0