Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15012745	0	0
ctrl_rd_A	2147483647	337276	0	0
intr_enable_rd_A	2147483647	300868	0	0
ovrd_rd_A	2147483647	335582	0	0
timeout_ctrl_rd_A	2147483647	337132	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15012745	0	0
T14	206965	79551	0	0
T15	481616	0	0	0
T16	0	218835	0	0
T19	372714	0	0	0
T20	0	158508	0	0
T24	533946	104662	0	0
T25	175461	0	0	0
T31	0	245730	0	0
T32	0	201129	0	0
T33	0	263458	0	0
T34	0	52175	0	0
T35	0	148011	0	0
T36	0	165003	0	0
T37	451964	0	0	0
T38	134149	0	0	0
T39	228043	0	0	0
T40	115492	0	0	0
T41	102246	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	337276	0	0
T34	228410	5395	0	0
T56	0	21347	0	0
T106	0	25098	0	0
T107	0	2508	0	0
T108	0	5965	0	0
T109	0	4624	0	0
T110	0	17807	0	0
T111	0	8427	0	0
T112	0	6873	0	0
T113	0	5821	0	0
T114	152663	0	0	0
T115	38202	0	0	0
T116	296068	0	0	0
T117	160476	0	0	0
T118	482308	0	0	0
T119	926	0	0	0
T120	185416	0	0	0
T121	858	0	0	0
T122	430868	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	300868	0	0
T34	228410	4819	0	0
T56	0	19986	0	0
T106	0	22548	0	0
T107	0	2168	0	0
T108	0	5028	0	0
T109	0	3971	0	0
T110	0	15352	0	0
T111	0	7715	0	0
T112	0	6174	0	0
T114	152663	0	0	0
T115	38202	0	0	0
T116	296068	0	0	0
T117	160476	0	0	0
T118	482308	0	0	0
T119	926	0	0	0
T120	185416	0	0	0
T121	858	0	0	0
T122	430868	0	0	0
T123	0	10	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	335582	0	0
T34	228410	5415	0	0
T56	0	21988	0	0
T106	0	25386	0	0
T107	0	2286	0	0
T108	0	6176	0	0
T109	0	4719	0	0
T110	0	17372	0	0
T111	0	8668	0	0
T112	0	6874	0	0
T113	0	5195	0	0
T114	152663	0	0	0
T115	38202	0	0	0
T116	296068	0	0	0
T117	160476	0	0	0
T118	482308	0	0	0
T119	926	0	0	0
T120	185416	0	0	0
T121	858	0	0	0
T122	430868	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	337132	0	0
T34	228410	5506	0	0
T56	0	22086	0	0
T106	0	25011	0	0
T107	0	2225	0	0
T108	0	6118	0	0
T109	0	4316	0	0
T110	0	18037	0	0
T111	0	8647	0	0
T112	0	6795	0	0
T113	0	5703	0	0
T114	152663	0	0	0
T115	38202	0	0	0
T116	296068	0	0	0
T117	160476	0	0	0
T118	482308	0	0	0
T119	926	0	0	0
T120	185416	0	0	0
T121	858	0	0	0
T122	430868	0	0	0