Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	13257726	0	0
ctrl_rd_A	2147483647	262859	0	0
intr_enable_rd_A	2147483647	232178	0	0
ovrd_rd_A	2147483647	261346	0	0
timeout_ctrl_rd_A	2147483647	261831	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13257726	0	0
T2	190481	45060	0	0
T3	954249	0	0	0
T4	109318	0	0	0
T5	581363	0	0	0
T6	442254	0	0	0
T7	147577	0	0	0
T8	562306	0	0	0
T9	358500	84815	0	0
T10	353313	0	0	0
T12	0	100053	0	0
T18	0	246259	0	0
T25	0	169154	0	0
T26	0	273748	0	0
T27	0	153223	0	0
T28	0	81705	0	0
T29	0	80963	0	0
T30	0	104639	0	0
T31	58315	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	262859	0	0
T2	190481	5184	0	0
T3	954249	0	0	0
T4	109318	0	0	0
T5	581363	0	0	0
T6	442254	0	0	0
T7	147577	0	0	0
T8	562306	0	0	0
T9	358500	10183	0	0
T10	353313	0	0	0
T12	0	11247	0	0
T27	0	8428	0	0
T28	0	9243	0	0
T31	58315	0	0	0
T46	0	10092	0	0
T50	0	26252	0	0
T51	0	12416	0	0
T107	0	2841	0	0
T108	0	3287	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	232178	0	0
T2	190481	4598	0	0
T3	954249	0	0	0
T4	109318	0	0	0
T5	581363	0	0	0
T6	442254	0	0	0
T7	147577	0	0	0
T8	562306	0	0	0
T9	358500	8571	0	0
T10	353313	0	0	0
T12	0	9900	0	0
T27	0	6842	0	0
T28	0	8054	0	0
T31	58315	0	0	0
T46	0	8887	0	0
T50	0	23653	0	0
T51	0	10505	0	0
T107	0	2431	0	0
T108	0	2998	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	261346	0	0
T2	190481	4761	0	0
T3	954249	0	0	0
T4	109318	0	0	0
T5	581363	0	0	0
T6	442254	0	0	0
T7	147577	0	0	0
T8	562306	0	0	0
T9	358500	10143	0	0
T10	353313	0	0	0
T12	0	11641	0	0
T27	0	7816	0	0
T28	0	8831	0	0
T31	58315	0	0	0
T46	0	9588	0	0
T50	0	26636	0	0
T51	0	12508	0	0
T107	0	2810	0	0
T108	0	3274	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	261831	0	0
T2	190481	5559	0	0
T3	954249	0	0	0
T4	109318	0	0	0
T5	581363	0	0	0
T6	442254	0	0	0
T7	147577	0	0	0
T8	562306	0	0	0
T9	358500	9757	0	0
T10	353313	0	0	0
T12	0	11114	0	0
T27	0	8029	0	0
T28	0	9139	0	0
T31	58315	0	0	0
T46	0	9751	0	0
T50	0	26795	0	0
T51	0	12957	0	0
T107	0	2723	0	0
T108	0	3370	0	0