Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	81197851	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30808627

1

T1

153

T2

47147

T3

134

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	102117046	1			T1	10628		T2	643204		T3	4096
values[0x0]	4672942	1			T1	180		T2	2241		T3	125
values[0x1]	5216490	1			T1	197		T2	2164		T3	104

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56313031	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

55693447

1

T1

3746

T2

240659

T3

1491

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	399874	1			T2	2531		T4	3604		T6	2
valid_sources[0x01]	421465	1			T2	2581		T4	3558		T6	1
valid_sources[0x02]	410345	1			T2	2391		T4	3570		T6	1
valid_sources[0x03]	380509	1			T2	2609		T4	3604		T6	1
valid_sources[0x04]	463272	1			T2	2490		T4	3588		T6	1
valid_sources[0x05]	394681	1			T2	2635		T4	3688		T6	1
valid_sources[0x06]	455531	1			T2	2427		T4	3630		T6	1
valid_sources[0x07]	435496	1			T2	2551		T4	3735		T7	1950
valid_sources[0x08]	394171	1			T2	2396		T4	3884		T7	1601
valid_sources[0x09]	442052	1			T2	2419		T4	3755		T6	1
valid_sources[0x0a]	381725	1			T2	2611		T4	3781		T6	1
valid_sources[0x0b]	484208	1			T2	2587		T4	3780		T6	3
valid_sources[0x0c]	449325	1			T2	2554		T4	3725		T6	1
valid_sources[0x0d]	460199	1			T2	2442		T4	3810		T7	1863
valid_sources[0x0e]	478118	1			T2	2572		T4	3652		T7	1470
valid_sources[0x0f]	474065	1			T2	2420		T4	3692		T6	2
valid_sources[0x10]	431416	1			T2	2340		T4	3777		T6	3
valid_sources[0x11]	425738	1			T2	2546		T4	3574		T7	1710
valid_sources[0x12]	403098	1			T2	2604		T4	3712		T6	1
valid_sources[0x13]	435572	1			T2	2460		T4	3571		T6	2
valid_sources[0x14]	473286	1			T2	2562		T4	3711		T5	3
valid_sources[0x15]	405780	1			T2	2623		T4	3686		T6	3
valid_sources[0x16]	524988	1			T2	2679		T4	3740		T6	1
valid_sources[0x17]	404439	1			T2	2602		T4	3677		T7	1573
valid_sources[0x18]	507529	1			T2	2612		T4	3665		T6	1
valid_sources[0x19]	394806	1			T2	2627		T4	3626		T6	1
valid_sources[0x1a]	422877	1			T2	2433		T4	3689		T7	1807
valid_sources[0x1b]	446521	1			T2	2476		T4	3761		T7	1626
valid_sources[0x1c]	499968	1			T2	2577		T4	3702		T6	1
valid_sources[0x1d]	406213	1			T2	2521		T4	3801		T6	1
valid_sources[0x1e]	447518	1			T2	2495		T4	3686		T6	1
valid_sources[0x1f]	441199	1			T2	2383		T4	3691		T7	1625
valid_sources[0x20]	427539	1			T2	2538		T4	3556		T6	1
valid_sources[0x21]	401010	1			T2	2560		T4	3850		T7	1714
valid_sources[0x22]	396840	1			T2	2698		T4	3639		T7	1682
valid_sources[0x23]	463329	1			T2	2544		T4	3714		T6	1
valid_sources[0x24]	421603	1			T2	2622		T4	3671		T6	1
valid_sources[0x25]	405060	1			T2	2571		T4	3665		T6	1
valid_sources[0x26]	433790	1			T2	2380		T3	1		T4	3707
valid_sources[0x27]	403036	1			T2	2437		T4	3708		T7	2058
valid_sources[0x28]	480209	1			T2	2533		T4	3734		T7	1837
valid_sources[0x29]	391442	1			T2	2723		T4	3647		T6	1
valid_sources[0x2a]	396657	1			T2	2568		T4	3619		T7	1914
valid_sources[0x2b]	426871	1			T2	2455		T4	3698		T6	2
valid_sources[0x2c]	424872	1			T2	2377		T4	3573		T7	1971
valid_sources[0x2d]	416408	1			T2	2587		T4	3806		T6	1
valid_sources[0x2e]	430155	1			T2	2603		T4	3779		T7	1945
valid_sources[0x2f]	446089	1			T2	2389		T4	3747		T6	1
valid_sources[0x30]	413819	1			T2	2531		T4	3564		T7	1858
valid_sources[0x31]	395207	1			T2	2342		T4	3673		T7	1779
valid_sources[0x32]	410440	1			T2	2417		T4	3703		T6	1
valid_sources[0x33]	437123	1			T2	2430		T4	3630		T6	1
valid_sources[0x34]	404823	1			T2	2464		T4	3633		T7	1427
valid_sources[0x35]	526461	1			T2	2393		T4	3636		T6	1
valid_sources[0x36]	521484	1			T2	2547		T4	3658		T7	1745
valid_sources[0x37]	391427	1			T2	2423		T4	3765		T7	1350
valid_sources[0x38]	419287	1			T2	2803		T4	3575		T7	1654
valid_sources[0x39]	497813	1			T2	2520		T4	3731		T6	1
valid_sources[0x3a]	408074	1			T2	2339		T4	3621		T6	2
valid_sources[0x3b]	452797	1			T2	2644		T4	3684		T6	1
valid_sources[0x3c]	419168	1			T2	2728		T4	3710		T7	1723
valid_sources[0x3d]	507934	1			T2	2725		T4	3770		T7	1755
valid_sources[0x3e]	451427	1			T2	2465		T4	3683		T7	1830
valid_sources[0x3f]	386038	1			T2	2657		T4	3737		T6	4
valid_sources[0x40]	518423	1			T2	2605		T4	3747		T6	4
valid_sources[0x41]	410068	1			T2	2606		T4	3769		T6	3
valid_sources[0x42]	406950	1			T2	2451		T4	3776		T7	2034
valid_sources[0x43]	431321	1			T2	2374		T4	3572		T7	1889
valid_sources[0x44]	453060	1			T2	2516		T4	3632		T7	1648
valid_sources[0x45]	406226	1			T2	2563		T4	3668		T6	1
valid_sources[0x46]	428745	1			T2	2430		T4	3666		T6	1
valid_sources[0x47]	454499	1			T2	2520		T4	3654		T6	1
valid_sources[0x48]	412781	1			T2	2604		T4	3535		T6	3
valid_sources[0x49]	432768	1			T2	2525		T4	3575		T7	1616
valid_sources[0x4a]	463239	1			T2	2496		T4	3600		T6	1
valid_sources[0x4b]	476031	1			T2	2472		T4	3700		T6	1
valid_sources[0x4c]	472166	1			T2	2330		T4	3600		T7	1889
valid_sources[0x4d]	409542	1			T2	2531		T4	3772		T6	1
valid_sources[0x4e]	450951	1			T2	2816		T4	3764		T6	1
valid_sources[0x4f]	419008	1			T2	2460		T4	3590		T6	1
valid_sources[0x50]	434744	1			T2	2585		T4	3734		T6	1
valid_sources[0x51]	459530	1			T2	2519		T4	3716		T7	1534
valid_sources[0x52]	385279	1			T2	2274		T4	3630		T6	1
valid_sources[0x53]	485381	1			T2	2627		T4	3648		T6	1
valid_sources[0x54]	411129	1			T2	2451		T4	3706		T7	1669
valid_sources[0x55]	468307	1			T2	2484		T4	3671		T6	2
valid_sources[0x56]	497345	1			T2	2428		T4	3546		T7	1895
valid_sources[0x57]	422889	1			T2	2736		T4	3582		T6	1
valid_sources[0x58]	410487	1			T1	4457		T2	2836		T4	3644
valid_sources[0x59]	536829	1			T2	2509		T4	3746		T6	1
valid_sources[0x5a]	439297	1			T2	2446		T4	3722		T6	3
valid_sources[0x5b]	540988	1			T2	2551		T4	3763		T7	1755
valid_sources[0x5c]	424383	1			T2	2743		T4	3677		T6	1
valid_sources[0x5d]	417040	1			T2	2495		T4	3698		T7	1632
valid_sources[0x5e]	442245	1			T2	2723		T4	3867		T6	2
valid_sources[0x5f]	481930	1			T2	2612		T4	3690		T6	4
valid_sources[0x60]	401189	1			T1	2316		T2	2536		T4	3669
valid_sources[0x61]	431345	1			T2	2505		T4	3592		T6	6
valid_sources[0x62]	419126	1			T2	2537		T4	3660		T6	2
valid_sources[0x63]	433583	1			T2	2523		T4	3598		T6	1
valid_sources[0x64]	585590	1			T2	2803		T4	3767		T6	2
valid_sources[0x65]	423781	1			T2	2438		T4	3688		T6	2
valid_sources[0x66]	464636	1			T2	2571		T4	3705		T7	1671
valid_sources[0x67]	393568	1			T2	2358		T4	3667		T6	1
valid_sources[0x68]	428000	1			T2	2545		T4	3682		T7	1945
valid_sources[0x69]	404087	1			T2	2487		T4	3703		T7	1697
valid_sources[0x6a]	443959	1			T2	2565		T4	3769		T6	1
valid_sources[0x6b]	405166	1			T2	2481		T4	3720		T6	4
valid_sources[0x6c]	427418	1			T2	2752		T4	3675		T7	1757
valid_sources[0x6d]	544748	1			T2	2635		T4	3787		T7	1868
valid_sources[0x6e]	492058	1			T1	4232		T2	2460		T4	3563
valid_sources[0x6f]	520528	1			T2	2562		T4	3692		T6	1
valid_sources[0x70]	455897	1			T2	2600		T4	3617		T7	1734
valid_sources[0x71]	507282	1			T2	2389		T4	3797		T7	1733
valid_sources[0x72]	401592	1			T2	2552		T4	3715		T6	1
valid_sources[0x73]	435619	1			T2	2473		T4	3623		T6	1
valid_sources[0x74]	401000	1			T2	2541		T4	3706		T7	1718
valid_sources[0x75]	412314	1			T2	2486		T4	3686		T6	3
valid_sources[0x76]	405320	1			T2	2526		T4	3664		T7	1725
valid_sources[0x77]	425581	1			T2	2595		T4	3624		T6	1
valid_sources[0x78]	486408	1			T2	2666		T4	3696		T6	1
valid_sources[0x79]	429107	1			T2	2455		T4	3815		T6	2
valid_sources[0x7a]	432584	1			T2	2468		T4	3620		T6	1
valid_sources[0x7b]	482499	1			T2	2462		T4	3681		T7	1662
valid_sources[0x7c]	563558	1			T2	2514		T4	3667		T7	1881
valid_sources[0x7d]	395675	1			T2	2486		T4	3616		T6	3
valid_sources[0x7e]	402362	1			T2	2602		T4	3695		T7	1704
valid_sources[0x7f]	556618	1			T2	2650		T4	3667		T7	1643
valid_sources[0x80]	419523	1			T2	2467		T4	3697		T7	1893

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22069835

1

T1

40

T2

46016

T3

70

values[0x0]

all_enables

biggest_size

4399504

1

T1

70

T2

761

T3

46

values[0x1]

all_enables

biggest_size

4339288

1

T1

43

T2

370

T3

18