Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14501005	0	0
ctrl_rd_A	2147483647	230682	0	0
intr_enable_rd_A	2147483647	207597	0	0
ovrd_rd_A	2147483647	231644	0	0
timeout_ctrl_rd_A	2147483647	232312	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14501005	0	0
T15	294559	87915	0	0
T16	0	144664	0	0
T17	0	145561	0	0
T22	0	243291	0	0
T24	53054	0	0	0
T27	270963	0	0	0
T34	0	101942	0	0
T35	0	160341	0	0
T36	0	79031	0	0
T37	0	373396	0	0
T38	0	167440	0	0
T39	0	24892	0	0
T40	13781	0	0	0
T41	140775	0	0	0
T42	10148	0	0	0
T43	326852	0	0	0
T44	158971	0	0	0
T45	157582	0	0	0
T46	207579	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	230682	0	0
T15	294559	4375	0	0
T17	0	7349	0	0
T24	53054	0	0	0
T27	270963	0	0	0
T35	0	18143	0	0
T38	0	7171	0	0
T40	13781	0	0	0
T41	140775	0	0	0
T42	10148	0	0	0
T43	326852	0	0	0
T44	158971	0	0	0
T45	157582	0	0	0
T46	207579	0	0	0
T108	0	4897	0	0
T109	0	4127	0	0
T110	0	8309	0	0
T111	0	5429	0	0
T112	0	7011	0	0
T113	0	44045	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	207597	0	0
T15	294559	4173	0	0
T17	0	6553	0	0
T24	53054	0	0	0
T27	270963	0	0	0
T35	0	16271	0	0
T38	0	6326	0	0
T40	13781	0	0	0
T41	140775	0	0	0
T42	10148	0	0	0
T43	326852	0	0	0
T44	158971	0	0	0
T45	157582	0	0	0
T46	207579	0	0	0
T108	0	4877	0	0
T109	0	3844	0	0
T110	0	7526	0	0
T111	0	4866	0	0
T112	0	6288	0	0
T113	0	39071	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	231644	0	0
T15	294559	4259	0	0
T17	0	7461	0	0
T24	53054	0	0	0
T27	270963	0	0	0
T35	0	18472	0	0
T38	0	7631	0	0
T40	13781	0	0	0
T41	140775	0	0	0
T42	10148	0	0	0
T43	326852	0	0	0
T44	158971	0	0	0
T45	157582	0	0	0
T46	207579	0	0	0
T108	0	5260	0	0
T109	0	4066	0	0
T110	0	8308	0	0
T111	0	5579	0	0
T112	0	6992	0	0
T113	0	43557	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	232312	0	0
T15	294559	4194	0	0
T17	0	7695	0	0
T24	53054	0	0	0
T27	270963	0	0	0
T35	0	18454	0	0
T38	0	7870	0	0
T40	13781	0	0	0
T41	140775	0	0	0
T42	10148	0	0	0
T43	326852	0	0	0
T44	158971	0	0	0
T45	157582	0	0	0
T46	207579	0	0	0
T108	0	5544	0	0
T109	0	4328	0	0
T110	0	8319	0	0
T111	0	5804	0	0
T112	0	7075	0	0
T113	0	44113	0	0