Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	80921945	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28885506

1

T1

163805

T2

3

T3

152

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	100396524	1			T1	169826		T2	1		T3	396
values[0x0]	4449247	1			T1	3218		T2	7		T3	113
values[0x1]	4961680	1			T1	3229		T2	13		T3	124

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56030962	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

53776489

1

T1

655327

T2

9

T3

274

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	424388	1			T1	6983		T4	53		T7	5
valid_sources[0x01]	509090	1			T1	6801		T4	54		T6	2
valid_sources[0x02]	409696	1			T1	6773		T4	80		T6	1
valid_sources[0x03]	397341	1			T1	6615		T4	66		T8	795
valid_sources[0x04]	411063	1			T1	6759		T4	90		T6	4
valid_sources[0x05]	415180	1			T1	6273		T4	92		T6	3
valid_sources[0x06]	586911	1			T1	6236		T4	53		T6	1
valid_sources[0x07]	396842	1			T1	6268		T4	72		T6	1
valid_sources[0x08]	404305	1			T1	6627		T4	95		T6	1
valid_sources[0x09]	417741	1			T1	6908		T4	84		T6	1
valid_sources[0x0a]	395576	1			T1	6809		T4	69		T6	3
valid_sources[0x0b]	392236	1			T1	6492		T4	52		T6	4
valid_sources[0x0c]	395071	1			T1	6334		T4	74		T7	10
valid_sources[0x0d]	394866	1			T1	6595		T4	73		T6	2
valid_sources[0x0e]	407241	1			T1	6226		T4	101		T5	1
valid_sources[0x0f]	419268	1			T1	6480		T4	62		T6	5
valid_sources[0x10]	436324	1			T1	7001		T4	59		T6	2
valid_sources[0x11]	438724	1			T1	6625		T4	72		T6	2
valid_sources[0x12]	460415	1			T1	6651		T4	75		T6	5
valid_sources[0x13]	447925	1			T1	6338		T4	49		T7	4
valid_sources[0x14]	402892	1			T1	6606		T4	53		T6	7
valid_sources[0x15]	405195	1			T1	5997		T4	83		T6	3
valid_sources[0x16]	396769	1			T1	6447		T4	52		T6	1
valid_sources[0x17]	436134	1			T1	6816		T4	70		T6	2
valid_sources[0x18]	403832	1			T1	6801		T4	81		T6	2
valid_sources[0x19]	405547	1			T1	6376		T4	64		T7	3
valid_sources[0x1a]	417498	1			T1	6405		T4	104		T6	3
valid_sources[0x1b]	437773	1			T1	6749		T4	78		T6	5
valid_sources[0x1c]	432843	1			T1	6909		T4	78		T6	8
valid_sources[0x1d]	406626	1			T1	6880		T4	83		T7	2
valid_sources[0x1e]	407430	1			T1	6865		T4	64		T7	11
valid_sources[0x1f]	452728	1			T1	6575		T4	83		T6	4
valid_sources[0x20]	427641	1			T1	6358		T4	81		T6	3
valid_sources[0x21]	402962	1			T1	6951		T4	53		T7	7
valid_sources[0x22]	397025	1			T1	6474		T4	72		T6	3
valid_sources[0x23]	411957	1			T1	6649		T4	57		T6	2
valid_sources[0x24]	401822	1			T1	6516		T4	69		T7	2
valid_sources[0x25]	397615	1			T1	6751		T4	56		T6	2
valid_sources[0x26]	486753	1			T1	6694		T4	73		T6	2
valid_sources[0x27]	380736	1			T1	6255		T4	73		T7	3
valid_sources[0x28]	405554	1			T1	7040		T4	75		T6	2
valid_sources[0x29]	461005	1			T1	6795		T4	71		T6	2
valid_sources[0x2a]	406737	1			T1	7055		T4	92		T6	6
valid_sources[0x2b]	432344	1			T1	6835		T4	78		T6	1
valid_sources[0x2c]	375166	1			T1	6292		T4	50		T6	2
valid_sources[0x2d]	443688	1			T1	6316		T4	63		T6	5
valid_sources[0x2e]	450975	1			T1	6389		T4	69		T6	2
valid_sources[0x2f]	616891	1			T1	6365		T4	98		T6	2
valid_sources[0x30]	546092	1			T1	6736		T4	57		T6	5
valid_sources[0x31]	416450	1			T1	6847		T4	51		T6	5
valid_sources[0x32]	445943	1			T1	6370		T4	61		T7	5
valid_sources[0x33]	444698	1			T1	6621		T4	91		T6	3
valid_sources[0x34]	483499	1			T1	6843		T4	94		T6	2
valid_sources[0x35]	465219	1			T1	7014		T4	66		T6	3
valid_sources[0x36]	395143	1			T1	6571		T4	75		T6	2
valid_sources[0x37]	483708	1			T1	6689		T4	56		T6	3
valid_sources[0x38]	410336	1			T1	6768		T4	61		T6	3
valid_sources[0x39]	398439	1			T1	6664		T4	64		T6	2
valid_sources[0x3a]	413596	1			T1	6490		T4	73		T6	4
valid_sources[0x3b]	548938	1			T1	6922		T4	69		T6	2
valid_sources[0x3c]	395681	1			T1	6338		T4	64		T7	1
valid_sources[0x3d]	407448	1			T1	6636		T4	68		T6	2
valid_sources[0x3e]	437182	1			T1	6487		T4	83		T6	3
valid_sources[0x3f]	400144	1			T1	6594		T4	75		T7	6
valid_sources[0x40]	384965	1			T1	6839		T4	119		T5	1
valid_sources[0x41]	455838	1			T1	7419		T4	75		T7	10
valid_sources[0x42]	487605	1			T1	6346		T4	95		T6	2
valid_sources[0x43]	406727	1			T1	7063		T4	71		T6	1
valid_sources[0x44]	436834	1			T1	6709		T4	71		T6	2
valid_sources[0x45]	391826	1			T1	6799		T4	72		T6	2
valid_sources[0x46]	401756	1			T1	6346		T4	77		T6	7
valid_sources[0x47]	397220	1			T1	6599		T4	82		T5	1
valid_sources[0x48]	396579	1			T1	6414		T4	65		T6	3
valid_sources[0x49]	411808	1			T1	6526		T4	62		T6	1
valid_sources[0x4a]	395143	1			T1	7083		T4	53		T6	1
valid_sources[0x4b]	416621	1			T1	6194		T4	80		T6	3
valid_sources[0x4c]	511753	1			T1	6493		T4	79		T8	852
valid_sources[0x4d]	414608	1			T1	6664		T4	64		T6	4
valid_sources[0x4e]	481047	1			T1	7089		T4	74		T6	1
valid_sources[0x4f]	515588	1			T1	6605		T4	75		T7	3
valid_sources[0x50]	395482	1			T1	6841		T4	77		T6	3
valid_sources[0x51]	442122	1			T1	6528		T4	94		T8	892
valid_sources[0x52]	400836	1			T1	6470		T4	58		T6	2
valid_sources[0x53]	411554	1			T1	6695		T4	73		T8	858
valid_sources[0x54]	416726	1			T1	6688		T4	69		T6	1
valid_sources[0x55]	450240	1			T1	6819		T4	67		T6	2
valid_sources[0x56]	393474	1			T1	6278		T4	57		T6	3
valid_sources[0x57]	399355	1			T1	6398		T4	71		T6	1
valid_sources[0x58]	395792	1			T1	6446		T4	73		T6	4
valid_sources[0x59]	488290	1			T1	6519		T4	55		T6	5
valid_sources[0x5a]	436814	1			T1	6141		T4	72		T6	3
valid_sources[0x5b]	521504	1			T1	6213		T4	63		T7	2
valid_sources[0x5c]	400294	1			T1	7187		T4	56		T6	4
valid_sources[0x5d]	453721	1			T1	6564		T4	75		T8	768
valid_sources[0x5e]	395396	1			T1	6444		T4	56		T6	2
valid_sources[0x5f]	446237	1			T1	5960		T4	80		T6	5
valid_sources[0x60]	520446	1			T1	6913		T4	59		T6	3
valid_sources[0x61]	393994	1			T1	6908		T3	632		T4	52
valid_sources[0x62]	405614	1			T1	6917		T4	77		T6	1
valid_sources[0x63]	428541	1			T1	6500		T4	50		T6	1
valid_sources[0x64]	477347	1			T1	6506		T4	81		T6	5
valid_sources[0x65]	406793	1			T1	6158		T4	77		T6	1
valid_sources[0x66]	387344	1			T1	6834		T4	60		T6	4
valid_sources[0x67]	411993	1			T1	6484		T4	72		T6	2
valid_sources[0x68]	403740	1			T1	6598		T4	56		T6	1
valid_sources[0x69]	410673	1			T1	6401		T4	67		T6	1
valid_sources[0x6a]	401252	1			T1	6756		T4	67		T5	1
valid_sources[0x6b]	393702	1			T1	6356		T4	80		T7	9
valid_sources[0x6c]	430990	1			T1	6815		T4	78		T6	4
valid_sources[0x6d]	419583	1			T1	6779		T4	80		T5	1
valid_sources[0x6e]	384391	1			T1	6821		T4	53		T6	4
valid_sources[0x6f]	377238	1			T1	6778		T2	1		T4	49
valid_sources[0x70]	385518	1			T1	6734		T4	63		T7	1
valid_sources[0x71]	404176	1			T1	6258		T4	78		T6	4
valid_sources[0x72]	494409	1			T1	6912		T2	3		T4	62
valid_sources[0x73]	434461	1			T1	6627		T4	93		T6	2
valid_sources[0x74]	415328	1			T1	6837		T4	86		T6	3
valid_sources[0x75]	406250	1			T1	6628		T4	67		T6	1
valid_sources[0x76]	518582	1			T1	6826		T4	54		T5	1
valid_sources[0x77]	402564	1			T1	6788		T4	55		T6	5
valid_sources[0x78]	416400	1			T1	7225		T4	73		T6	2
valid_sources[0x79]	414199	1			T1	7412		T4	55		T6	1
valid_sources[0x7a]	533875	1			T1	6570		T4	51		T7	7
valid_sources[0x7b]	419676	1			T1	6213		T4	90		T6	2
valid_sources[0x7c]	411603	1			T1	6652		T4	83		T7	6
valid_sources[0x7d]	412072	1			T1	7036		T2	1		T4	90
valid_sources[0x7e]	392182	1			T1	6444		T4	61		T6	2
valid_sources[0x7f]	420968	1			T1	6510		T4	59		T6	1
valid_sources[0x80]	428420	1			T1	6741		T4	54		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20607562

1

T1

162158

T3

86

T4

124

values[0x0]

all_enables

biggest_size

4172768

1

T1

1092

T2

3

T3

39

values[0x1]

all_enables

biggest_size

4105176

1

T1

555

T3

27

T4

34