Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	13756762	0	0
ctrl_rd_A	2147483647	180904	0	0
intr_enable_rd_A	2147483647	158243	0	0
ovrd_rd_A	2147483647	179163	0	0
timeout_ctrl_rd_A	2147483647	179190	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13756762	0	0
T8	211034	83681	0	0
T9	313545	0	0	0
T10	561115	0	0	0
T11	385372	0	0	0
T12	616745	0	0	0
T13	278594	0	0	0
T14	0	250409	0	0
T15	0	1809	0	0
T16	0	79227	0	0
T18	0	176868	0	0
T20	98557	0	0	0
T27	0	143200	0	0
T28	0	128747	0	0
T29	0	204678	0	0
T30	0	94298	0	0
T31	0	73646	0	0
T32	271725	0	0	0
T33	261268	0	0	0
T34	66004	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	180904	0	0
T15	65735	241	0	0
T16	196346	0	0	0
T37	255037	0	0	0
T51	0	6225	0	0
T112	0	8323	0	0
T113	0	5047	0	0
T114	0	5549	0	0
T115	0	2092	0	0
T116	0	9837	0	0
T117	0	5538	0	0
T118	0	14602	0	0
T119	0	7410	0	0
T120	101744	0	0	0
T121	230541	0	0	0
T122	213694	0	0	0
T123	555581	0	0	0
T124	483261	0	0	0
T125	842892	0	0	0
T126	227272	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	158243	0	0
T15	65735	214	0	0
T16	196346	0	0	0
T37	255037	0	0	0
T51	0	5420	0	0
T112	0	7425	0	0
T113	0	4320	0	0
T114	0	4953	0	0
T115	0	1889	0	0
T116	0	8500	0	0
T117	0	4554	0	0
T118	0	12429	0	0
T119	0	6567	0	0
T120	101744	0	0	0
T121	230541	0	0	0
T122	213694	0	0	0
T123	555581	0	0	0
T124	483261	0	0	0
T125	842892	0	0	0
T126	227272	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	179163	0	0
T15	65735	258	0	0
T16	196346	0	0	0
T37	255037	0	0	0
T51	0	6764	0	0
T112	0	7849	0	0
T113	0	4959	0	0
T114	0	5419	0	0
T115	0	2119	0	0
T116	0	9576	0	0
T117	0	5694	0	0
T118	0	14232	0	0
T119	0	7316	0	0
T120	101744	0	0	0
T121	230541	0	0	0
T122	213694	0	0	0
T123	555581	0	0	0
T124	483261	0	0	0
T125	842892	0	0	0
T126	227272	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	179190	0	0
T15	65735	214	0	0
T16	196346	0	0	0
T37	255037	0	0	0
T51	0	6400	0	0
T112	0	8616	0	0
T113	0	5117	0	0
T114	0	5521	0	0
T115	0	1899	0	0
T116	0	9750	0	0
T117	0	5462	0	0
T118	0	14864	0	0
T119	0	7302	0	0
T120	101744	0	0	0
T121	230541	0	0	0
T122	213694	0	0	0
T123	555581	0	0	0
T124	483261	0	0	0
T125	842892	0	0	0
T126	227272	0	0	0