Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14388125	0	0
ctrl_rd_A	2147483647	298224	0	0
intr_enable_rd_A	2147483647	266815	0	0
ovrd_rd_A	2147483647	297445	0	0
timeout_ctrl_rd_A	2147483647	296634	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14388125	0	0
T6	159060	40758	0	0
T7	805341	0	0	0
T8	259654	0	0	0
T9	690169	0	0	0
T10	333920	0	0	0
T11	288697	0	0	0
T12	301735	0	0	0
T13	710112	0	0	0
T14	0	215648	0	0
T16	0	132630	0	0
T26	0	117987	0	0
T27	0	135758	0	0
T28	0	172376	0	0
T29	0	315583	0	0
T30	0	154410	0	0
T31	0	32193	0	0
T32	0	161959	0	0
T33	203794	0	0	0
T34	509136	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	298224	0	0
T6	159060	3986	0	0
T7	805341	0	0	0
T8	259654	0	0	0
T9	690169	0	0	0
T10	333920	0	0	0
T11	288697	0	0	0
T12	301735	0	0	0
T13	710112	0	0	0
T16	0	14756	0	0
T33	203794	0	0	0
T34	509136	0	0	0
T47	0	5728	0	0
T50	0	7311	0	0
T52	0	14344	0	0
T104	0	7864	0	0
T105	0	3634	0	0
T106	0	2658	0	0
T107	0	1404	0	0
T108	0	9704	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	266815	0	0
T6	159060	3781	0	0
T7	805341	0	0	0
T8	259654	0	0	0
T9	690169	0	0	0
T10	333920	0	0	0
T11	288697	0	0	0
T12	301735	0	0	0
T13	710112	0	0	0
T16	0	13148	0	0
T33	203794	0	0	0
T34	509136	0	0	0
T47	0	4975	0	0
T50	0	6870	0	0
T52	0	13125	0	0
T104	0	7293	0	0
T105	0	3013	0	0
T106	0	2128	0	0
T109	0	13	0	0
T110	0	7	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	297445	0	0
T6	159060	4032	0	0
T7	805341	0	0	0
T8	259654	0	0	0
T9	690169	0	0	0
T10	333920	0	0	0
T11	288697	0	0	0
T12	301735	0	0	0
T13	710112	0	0	0
T16	0	14686	0	0
T33	203794	0	0	0
T34	509136	0	0	0
T47	0	5466	0	0
T50	0	7702	0	0
T52	0	14576	0	0
T104	0	7985	0	0
T105	0	3568	0	0
T106	0	2543	0	0
T107	0	1247	0	0
T108	0	9764	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	296634	0	0
T6	159060	4112	0	0
T7	805341	0	0	0
T8	259654	0	0	0
T9	690169	0	0	0
T10	333920	0	0	0
T11	288697	0	0	0
T12	301735	0	0	0
T13	710112	0	0	0
T16	0	15124	0	0
T33	203794	0	0	0
T34	509136	0	0	0
T47	0	5659	0	0
T50	0	7714	0	0
T52	0	13647	0	0
T104	0	7287	0	0
T105	0	3829	0	0
T106	0	2588	0	0
T107	0	1251	0	0
T108	0	9937	0	0