Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : uart_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.06 98.77 98.68 100.00 97.85 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_ctrl_llpbk 100.00 100.00 100.00 100.00
u_ctrl_nco 100.00 100.00 100.00 100.00
u_ctrl_nf 100.00 100.00 100.00 100.00
u_ctrl_parity_en 100.00 100.00 100.00 100.00
u_ctrl_parity_odd 100.00 100.00 100.00 100.00
u_ctrl_rx 100.00 100.00 100.00 100.00
u_ctrl_rxblvl 100.00 100.00 100.00 100.00
u_ctrl_slpbk 100.00 100.00 100.00 100.00
u_ctrl_tx 100.00 100.00 100.00 100.00
u_fifo_ctrl0_qe 100.00 100.00 100.00
u_fifo_ctrl_rxilvl 96.30 100.00 88.89 100.00
u_fifo_ctrl_rxrst 100.00 100.00 100.00 100.00
u_fifo_ctrl_txilvl 96.30 100.00 88.89 100.00
u_fifo_ctrl_txrst 100.00 100.00 100.00 100.00
u_fifo_status_rxlvl 100.00 100.00
u_fifo_status_txlvl 100.00 100.00
u_intr_enable_rx_break_err 100.00 100.00 100.00 100.00
u_intr_enable_rx_frame_err 100.00 100.00 100.00 100.00
u_intr_enable_rx_overflow 100.00 100.00 100.00 100.00
u_intr_enable_rx_parity_err 100.00 100.00 100.00 100.00
u_intr_enable_rx_timeout 100.00 100.00 100.00 100.00
u_intr_enable_rx_watermark 100.00 100.00 100.00 100.00
u_intr_enable_tx_done 100.00 100.00 100.00 100.00
u_intr_enable_tx_empty 100.00 100.00 100.00 100.00
u_intr_enable_tx_watermark 100.00 100.00 100.00 100.00
u_intr_state_rx_break_err 100.00 100.00 100.00 100.00
u_intr_state_rx_frame_err 100.00 100.00 100.00 100.00
u_intr_state_rx_overflow 100.00 100.00 100.00 100.00
u_intr_state_rx_parity_err 100.00 100.00 100.00 100.00
u_intr_state_rx_timeout 100.00 100.00 100.00 100.00
u_intr_state_rx_watermark 62.59 77.78 50.00 60.00
u_intr_state_tx_done 100.00 100.00 100.00 100.00
u_intr_state_tx_empty 62.59 77.78 50.00 60.00
u_intr_state_tx_watermark 62.59 77.78 50.00 60.00
u_intr_test_rx_break_err 100.00 100.00
u_intr_test_rx_frame_err 100.00 100.00
u_intr_test_rx_overflow 100.00 100.00
u_intr_test_rx_parity_err 100.00 100.00
u_intr_test_rx_timeout 100.00 100.00
u_intr_test_rx_watermark 100.00 100.00
u_intr_test_tx_done 100.00 100.00
u_intr_test_tx_empty 100.00 100.00
u_intr_test_tx_watermark 100.00 100.00
u_ovrd_txen 100.00 100.00 100.00 100.00
u_ovrd_txval 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_rdata 100.00 100.00
u_reg_if 98.67 97.14 97.53 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_status_rxempty 100.00 100.00
u_status_rxfull 100.00 100.00
u_status_rxidle 100.00 100.00
u_status_txempty 100.00 100.00
u_status_txfull 100.00 100.00
u_status_txidle 100.00 100.00
u_timeout_ctrl_en 100.00 100.00 100.00 100.00
u_timeout_ctrl_val 100.00 100.00 100.00 100.00
u_val 100.00 100.00
u_wdata 100.00 100.00 100.00 100.00
u_wdata0_qe 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : uart_reg_top
Line No.TotalCoveredPercent
TOTAL172172100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN71811100.00
CONT_ASSIGN73311100.00
CONT_ASSIGN74911100.00
CONT_ASSIGN76511100.00
CONT_ASSIGN78111100.00
CONT_ASSIGN79711100.00
CONT_ASSIGN81311100.00
CONT_ASSIGN82911100.00
CONT_ASSIGN84511100.00
CONT_ASSIGN86111100.00
CONT_ASSIGN86711100.00
CONT_ASSIGN88111100.00
CONT_ASSIGN127411100.00
CONT_ASSIGN131511100.00
CONT_ASSIGN134311100.00
CONT_ASSIGN137111100.00
CONT_ASSIGN139911100.00
ALWAYS15651414100.00
CONT_ASSIGN158111100.00
ALWAYS158511100.00
CONT_ASSIGN160211100.00
CONT_ASSIGN160411100.00
CONT_ASSIGN160611100.00
CONT_ASSIGN160811100.00
CONT_ASSIGN161011100.00
CONT_ASSIGN161211100.00
CONT_ASSIGN161411100.00
CONT_ASSIGN161511100.00
CONT_ASSIGN161711100.00
CONT_ASSIGN161911100.00
CONT_ASSIGN162111100.00
CONT_ASSIGN162311100.00
CONT_ASSIGN162511100.00
CONT_ASSIGN162711100.00
CONT_ASSIGN162911100.00
CONT_ASSIGN163111100.00
CONT_ASSIGN163311100.00
CONT_ASSIGN163411100.00
CONT_ASSIGN163611100.00
CONT_ASSIGN163811100.00
CONT_ASSIGN164011100.00
CONT_ASSIGN164211100.00
CONT_ASSIGN164411100.00
CONT_ASSIGN164611100.00
CONT_ASSIGN164811100.00
CONT_ASSIGN165011100.00
CONT_ASSIGN165211100.00
CONT_ASSIGN165311100.00
CONT_ASSIGN165511100.00
CONT_ASSIGN165611100.00
CONT_ASSIGN165811100.00
CONT_ASSIGN166011100.00
CONT_ASSIGN166211100.00
CONT_ASSIGN166411100.00
CONT_ASSIGN166611100.00
CONT_ASSIGN166811100.00
CONT_ASSIGN167011100.00
CONT_ASSIGN167211100.00
CONT_ASSIGN167411100.00
CONT_ASSIGN167511100.00
CONT_ASSIGN167611100.00
CONT_ASSIGN167711100.00
CONT_ASSIGN167911100.00
CONT_ASSIGN168011100.00
CONT_ASSIGN168211100.00
CONT_ASSIGN168411100.00
CONT_ASSIGN168611100.00
CONT_ASSIGN168811100.00
CONT_ASSIGN168911100.00
CONT_ASSIGN169011100.00
CONT_ASSIGN169211100.00
CONT_ASSIGN169411100.00
CONT_ASSIGN169511100.00
CONT_ASSIGN169611100.00
CONT_ASSIGN169811100.00
CONT_ASSIGN170011100.00
ALWAYS17041414100.00
ALWAYS17225858100.00
CONT_ASSIGN183000
CONT_ASSIGN183811100.00
CONT_ASSIGN183911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
718 1 1
733 1 1
749 1 1
765 1 1
781 1 1
797 1 1
813 1 1
829 1 1
845 1 1
861 1 1
867 1 1
881 1 1
1274 1 1
1315 1 1
1343 1 1
1371 1 1
1399 1 1
1565 1 1
1566 1 1
1567 1 1
1568 1 1
1569 1 1
1570 1 1
1571 1 1
1572 1 1
1573 1 1
1574 1 1
1575 1 1
1576 1 1
1577 1 1
1578 1 1
1581 1 1
1585 1 1
1602 1 1
1604 1 1
1606 1 1
1608 1 1
1610 1 1
1612 1 1
1614 1 1
1615 1 1
1617 1 1
1619 1 1
1621 1 1
1623 1 1
1625 1 1
1627 1 1
1629 1 1
1631 1 1
1633 1 1
1634 1 1
1636 1 1
1638 1 1
1640 1 1
1642 1 1
1644 1 1
1646 1 1
1648 1 1
1650 1 1
1652 1 1
1653 1 1
1655 1 1
1656 1 1
1658 1 1
1660 1 1
1662 1 1
1664 1 1
1666 1 1
1668 1 1
1670 1 1
1672 1 1
1674 1 1
1675 1 1
1676 1 1
1677 1 1
1679 1 1
1680 1 1
1682 1 1
1684 1 1
1686 1 1
1688 1 1
1689 1 1
1690 1 1
1692 1 1
1694 1 1
1695 1 1
1696 1 1
1698 1 1
1700 1 1
1704 1 1
1705 1 1
1706 1 1
1707 1 1
1708 1 1
1709 1 1
1710 1 1
1711 1 1
1712 1 1
1713 1 1
1714 1 1
1715 1 1
1716 1 1
1717 1 1
1722 1 1
1723 1 1
1725 1 1
1726 1 1
1727 1 1
1728 1 1
1729 1 1
1730 1 1
1731 1 1
1732 1 1
1733 1 1
1737 1 1
1738 1 1
1739 1 1
1740 1 1
1741 1 1
1742 1 1
1743 1 1
1744 1 1
1745 1 1
1749 1 1
1750 1 1
1751 1 1
1752 1 1
1753 1 1
1754 1 1
1755 1 1
1756 1 1
1757 1 1
1761 1 1
1765 1 1
1766 1 1
1767 1 1
1768 1 1
1769 1 1
1770 1 1
1771 1 1
1772 1 1
1773 1 1
1777 1 1
1778 1 1
1779 1 1
1780 1 1
1781 1 1
1782 1 1
1786 1 1
1790 1 1
1794 1 1
1795 1 1
1796 1 1
1797 1 1
1801 1 1
1802 1 1
1806 1 1
1807 1 1
1811 1 1
1815 1 1
1816 1 1
1830 unreachable
1838 1 1
1839 1 1


Cond Coverage for Module : uart_reg_top
TotalCoveredPercent
Conditions153153100.00
Logical153153100.00
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T15,T18
11CoveredT1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT24,T25,T26
10CoveredT90,T91,T92

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT24,T25,T26
010CoveredT90,T91,T92
100CoveredT24,T25,T26

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT90,T91,T92
010CoveredT14,T15,T18
100CoveredT14,T15,T18

 LINE       1566
 EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_STATE_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1567
 EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       1568
 EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_TEST_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1569
 EXPRESSION (reg_addr == uart_reg_pkg::UART_ALERT_TEST_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       1570
 EXPRESSION (reg_addr == uart_reg_pkg::UART_CTRL_OFFSET)
            ----------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       1571
 EXPRESSION (reg_addr == uart_reg_pkg::UART_STATUS_OFFSET)
            -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1572
 EXPRESSION (reg_addr == uart_reg_pkg::UART_RDATA_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       1573
 EXPRESSION (reg_addr == uart_reg_pkg::UART_WDATA_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1574
 EXPRESSION (reg_addr == uart_reg_pkg::UART_FIFO_CTRL_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       1575
 EXPRESSION (reg_addr == uart_reg_pkg::UART_FIFO_STATUS_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1576
 EXPRESSION (reg_addr == uart_reg_pkg::UART_OVRD_OFFSET)
            ----------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T5

 LINE       1577
 EXPRESSION (reg_addr == uart_reg_pkg::UART_VAL_OFFSET)
            ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T14

 LINE       1578
 EXPRESSION (reg_addr == uart_reg_pkg::UART_TIMEOUT_CTRL_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       1581
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1581
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       1585
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT14,T15,T18

 LINE       1585
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))))
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTests
0000000000000CoveredT1,T2,T3
0000000000001CoveredT3,T14,T20
0000000000010CoveredT1,T3,T14
0000000000100CoveredT3,T14,T20
0000000001000CoveredT1,T2,T3
0000000010000CoveredT3,T14,T20
0000000100000CoveredT1,T3,T14
0000001000000CoveredT2,T3,T4
0000010000000CoveredT1,T3,T9
0000100000000CoveredT3,T14,T20
0001000000000CoveredT3,T14,T20
0010000000000CoveredT1,T3,T14
0100000000000CoveredT2,T3,T14
1000000000000CoveredT1,T2,T3

 LINE       1585
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1585
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T14

 LINE       1585
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T3,T14

 LINE       1585
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T14
11CoveredT3,T14,T20

 LINE       1585
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT3,T14,T20

 LINE       1585
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT1,T3,T9

 LINE       1585
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       1585
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT1,T3,T14

 LINE       1585
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT3,T14,T20

 LINE       1585
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T6
11CoveredT1,T2,T3

 LINE       1585
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT3,T14,T20

 LINE       1585
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T14,T20
11CoveredT1,T3,T14

 LINE       1585
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT3,T14,T20

 LINE       1602
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT14,T15,T18
111CoveredT2,T3,T4

 LINE       1615
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT14,T15,T18
111CoveredT2,T3,T4

 LINE       1634
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT14,T15,T18
111CoveredT2,T14,T15

 LINE       1653
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT1,T3,T14
110CoveredT14,T15,T18
111CoveredT1,T22,T23

 LINE       1656
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT14,T15,T18
111CoveredT2,T3,T4

 LINE       1675
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT91,T93,T94
111CoveredT2,T4,T5

 LINE       1676
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT90,T92,T94
111CoveredT2,T4,T5

 LINE       1677
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT14,T15,T18
111CoveredT2,T4,T5

 LINE       1680
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT14,T15,T18
111CoveredT2,T3,T4

 LINE       1689
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT95,T96,T97
111CoveredT2,T4,T6

 LINE       1690
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T5
110CoveredT14,T15,T18
111CoveredT2,T5,T14

 LINE       1695
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T14
110CoveredT98,T99
111CoveredT3,T14,T15

 LINE       1696
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT14,T15,T18
111CoveredT2,T3,T4

Branch Coverage for Module : uart_reg_top
Line No.TotalCoveredPercent
Branches 19 19 100.00
TERNARY 1581 2 2 100.00
IF 68 3 3 100.00
CASE 1723 14 14 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 1581 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T24,T25,T26
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1723 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T2,T3,T4
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T2,T3,T4
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T2,T3,T4
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T2,T3,T4
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T2,T3,T4
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T2,T3,T4
default Covered T1,T2,T3


Assert Coverage for Module : uart_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 2147483647 99664554 0 0
reAfterRv 2147483647 99664554 0 0
rePulse 2147483647 98328044 0 0
wePulse 2147483647 1336510 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 99664554 0 0
T1 1109 17 0 0
T2 526361 87536 0 0
T3 260408 23942 0 0
T4 441140 398 0 0
T5 152531 10093 0 0
T6 266418 2071 0 0
T7 228700 1693 0 0
T8 799277 5473 0 0
T9 133631 4504 0 0
T10 312948 1183 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 99664554 0 0
T1 1109 17 0 0
T2 526361 87536 0 0
T3 260408 23942 0 0
T4 441140 398 0 0
T5 152531 10093 0 0
T6 266418 2071 0 0
T7 228700 1693 0 0
T8 799277 5473 0 0
T9 133631 4504 0 0
T10 312948 1183 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 98328044 0 0
T1 1109 1 0 0
T2 526361 87368 0 0
T3 260408 23920 0 0
T4 441140 134 0 0
T5 152531 10041 0 0
T6 266418 1694 0 0
T7 228700 1256 0 0
T8 799277 5102 0 0
T9 133631 4141 0 0
T10 312948 1019 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1336510 0 0
T1 1109 16 0 0
T2 526361 168 0 0
T3 260408 22 0 0
T4 441140 264 0 0
T5 152531 52 0 0
T6 266418 377 0 0
T7 228700 437 0 0
T8 799277 371 0 0
T9 133631 363 0 0
T10 312948 164 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%